HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: 405CR (IBM)

 

Скачать: PDF   ZIP
IBM

Document Outline

4/11/03
PowerPC 405CR Embedded Processor Data Sheet
1
Features
IBM PowerPC
405 32-bit RISC processor core
operating up to 266MHz
- Memory Management Unit
- 16KB instruction and 8KB data caches
- Multiply-Accumulate (MAC) function,
including fast multiply unit
- Programmable Timers
PC-133 synchronous DRAM (SDRAM) interface
operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Up to eight devices
- External Mastering supported
DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
- Four channels
Programmable Interrupt Controller supports
interrupts from a variety of sources
- Supports 7 external and 10 internal
interrupts
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority
ordering
Two serial ports (16550 compatible UART)
One IIC interface
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
Description
The IBM PowerPC 405CR
(PPC405CR) is a 32-bit
RISC embedded controller. High performance,
peripheral integration, and low cost make the device
ideal for wired communications, network printers,
and other computing applications.
This device is an easy upgrade for systems based
on PowerPC 403xx embedded processors, while
providing a base for custom chip designs.
The controller is powered by a PPC405 embedded
core. This core tightly couples a 266 MHz CPU,
MMU, instruction and data caches, and debug logic.
Fine-tuning of the core reduces data transfer
overhead, minimizes pipeline stalls, and improves
performance.
The PPC405CR employs the IBM CoreConnect
bus architecture. This architecture, as implemented
on the PPC405CR, consists of a 64-bit, 133-MHz
Processor Local Bus (PLB) and a 32-bit, 66-MHz
On-Chip Peripheral Bus (OPB). High-performance
peripherals attach to the PLB and less performance-
critical peripherals attach to the OPB.
Technology: IBM CMOS SA-12E 0.25
m
(0.18
m L
eff
)
Package: 27mm, 316-ball enhanced plastic ball grid
array (E-PBGA)
Power (estimated): Typical 0.9 W, Maximum 2.0W
at 200MHz.
PowerPC 405CR Embedded Processor Data Sheet
2
4/11/03
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figures
PPC405CR Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
27mm, 316-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5V-Tolerant I/O Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PowerPC 405CR Embedded Processor Data Sheet
4/11/03
3
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O Specifications--All speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I/O Specifications--200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O Specifications--266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PowerPC 405CR Embedded Processor Data Sheet
4
4/11/03
Ordering, PVR, and JTAG Information
This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local
IBM sales office.
Each part number contains a revision code. This refers to the die mask revision number and is specified in
the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) is software accessible and contains additional information about the
revision level of the part. Refer to the
PPC405CR Embedded Processor User's Manual for details on the
register content.
IBM Part Number Key
Product Name
Order Part Number
1
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
PPC405CR
IBM25PPC405CR-3BC200C
200 MHz
27 mm, 316 E-PBGA
C
0x40110145
0x42051049
PPC405CR
IBM25PPC405CR-3BC200CZ
200 MHz
27 mm, 316 E-PBGA
C
0x40110145
0x42051049
PPC405CR
IBM25PPC405CR-3BC266C
266 MHz
27 mm, 316 E-PBGA
C
0x40110145
0x42051049
PPC405CR
IBM25PPC405CR-3BC266CZ
266 MHz
27 mm, 316 E-PBGA
C
0x40110145
0x42051049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
IBM Part Number
IBM25PPC405CR-3BC200Cx
Package (E-PBGA)
Processor Speed
Grade 3 Reliability
Operational Case Temperature
Revision Level
Shipping Package
Blank = Tray
Z = Tape and reel
(-40C to +85 C)
Range
200MHz
266MHz
PowerPC 405CR Embedded Processor Data Sheet
4/11/03
5
PPC405CR Embedded Controller Functional Block Diagram
The PPC405CR is designed using the IBM Microelectronics Blue Logic
methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnect
Bus Architecture.
PPC405
Processor Core
DCU
ICU
DCR Bus
16KB
On-chip Peripheral Bus (OPB)
GPIO
IIC
UART
UART
DMA
Bridge
Processor Local Bus (PLB)
SDRAM
Code
Decompression
External
Bus
Controller
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
Controller
OPB
Interrupt
Controller
Arb
32-bit addr
32-bit data
13-bit addr
32-bit data
External
Bus Master
Controller
Universal
I-Cache
8KB
D-Cache
(4-Channel)
(CodePack
)
DCRs
Arb
© 2018 • ChipFind
Контакты
Главная страница