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Datasheet: GM71CS16160CCL (Hynix Semiconductor)

1,048,576 Words X 16 Bit CMOS Dynamic RAM

 

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Hynix Semiconductor
4 2
4 3
4 4
4 5
4 6
4 0
4 1
3 3
3 0
3 1
3 2
2 7
2 8
2 9
2 6
3 4
3 5
3 6
4 7
4 8
4 9
5 0
NC
NC
V
S S
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O 9
I/O 8
V
S S
L C A S
U C A S
OE
A 8
A 7
A 6
A 5
A 4
V
S S
A 9
V
S S
I/O15
I/O14
I/O13
I/O12
3 8
3 9
4 0
4 1
4 2
I/O11
I/O10
I/O 9
I/O 8
NC
3 2
3 3
3 4
3 5
3 6
V
S S
3 7
L C A S
U C A S
OE
2 9
3 0
3 1
A 9
A 8
A 7
2 6
2 7
2 8
A 6
A 5
A 4
2 3
2 4
2 5
V
S S
2 2
T h e G M 7 1 C ( S ) 1 6 1 6 0 C /C L i s t h e n e w
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)16160C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)16160C/CL offers
Fast Page Mode as a high speed access mode.
M u l t i p l e x e d a d d r e s s i n p u t s p e r m i t t h e
G M 7 1 C ( S ) 1 6 1 6 0 C /C L t o b e p a c k a g e d i n
standard 400 mil 42 pin plastic SOJ , and
standard 400mil 44(50)pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
Description
F eatur es
* 1 ,048,576 Words x 16 Bit Organization
* Fast Page Mode Capability
* S ingle Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
P in Configuration
1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
GM71CS16160CL
(Unit: ns)
GM71C(S)16160C/CL-5
GM71C(S)16160C/CL-6
GM71C(S)16160C/CL-7
t
R A C
t
C A C
t
R C
t
PC
50
60
13
15
9 0
110
35
40
70
18
130
45
* Low Power
Active : 605/550/495mW (MAX)
S tandby : 11mW (CMOS level : MAX )
0.83mW (L-version : MAX )
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/64ms
* 4096 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* B attery B ack Up Operation (L-version)
* 2 CAS byte Control
(Top View)
1 1
1
2
3
4
5
7
8
9
1 0
6
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
NC
NC
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
C C
NC
W E
R A S
A11
A10
A 0
A 1
V
C C
V
C C
A 2
A 3
44(50) TSOP II
V
C C
I/O 0
I/O 1
I/O 2
I/O 3
1
2
3
4
5
I/O 4
I/O 5
I/O 6
I/O 7
NC
7
8
9
1 0
1 1
V
C C
6
NC
W E
R A S
1 2
1 3
1 4
A11
A10
A 0
1 5
1 6
1 7
A 1
A 2
A 3
1 8
1 9
2 0
V
C C
2 1
42 SOJ
GM71C16160C
Rev 0.1 / Apr'01
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr'01
P in Descr iption
P in
F unction
P in
F unction
C C
V
S S
NC
Address Inputs
Refresh Address Inputs
Data Input/ Data Output
Row Address Strobe
Read/W rite Enable
Power (+5V)
Ground
No Connection
Ordering Information
R A S
W E
Column Address Strobe
Output Enable
O E
Absolute Maximum Ratings*
P
D
1.0
Power Dissipation
W
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Symbol
Parameter
Rating
Unit
T
A
T
S T G
V
IN/OUT
V
C C
I
O U T
0 ~
+
70
-55 ~
+
125
50
Ambient Temperature under B ias
S torage Temperature (Plastic)
Voltage on any Pin Relative to V
S S
Voltage on V
C C
Relative to V
S S
Short Circuit Output Current
C
C
V
V
mA
-1.0 ~
+
7.0V
-1.0 ~
+
7.0V
T ype No.
Access Time
Package
GM71C(S)16160CJ/C L J - 5
GM71C(S)16160CJ/C L J - 6
GM71C(S)16160CJ/C L J - 7
50ns
60ns
70ns
400 Mil
42 Pin
Plastic SOJ
50ns
60ns
70ns
400 Mil
44(50) Pin
Plastic TSOP II
GM71C(S)16160CT/CLT -5
GM71C(S)16160CT/CLT -6
GM71C(S)16160CT/CLT -7
UCAS, LCAS
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr'01
T r uth Table
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.
t
W C S
>= 0ns Early write cycle
t
W C S
<= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
L C A S
H
L
L
L
D
H
L
H
D
H
H
L
D
H
H
H
D
D
L
L
Output
Open
Valid
Valid
Valid
Lower byte
Upper byte
Word
Operation
S tandby
RAS-only
Refresh cycle
Read cycle
L
L
L
L
L
L
H
L
H
Early write cycle
L
H
L
L
H
Open
Open
Open
L
L
L
L
Undefined
Delayed Write
cycle
L
L
L
H
H
H to L
L
C B R R e f resh
or
Self Refresh
(L-series)
H to L
H
L
H to L
L
L
RAS
UCAS
W E
O E
Notes
1,3
1,3
1,3
1,3
1,3
1,2,3
1,2,3
1,3
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Undefined
Undefined
Open
Open
Open
Open
Open
Valid
Valid
Valid
Word
Word
Word
Word
Read-modify
-write cycle
Read cycle
(Output disabled)
D
D
H to L
H to L
H to L
L
L
L
L
L
L
L
H
L
L
L
L
H
D
D
L
H
H
H
H
L
D
D
D
D
D
D
L to H
L to H
L to H
L
L
L
L
R ecommended DC Operating Conditions
(T
A
= 0 ~
+
70C)
Symbol
Parameter
Unit
V
C C
V
IH
V
IL
S upply Voltage
Input High Voltage
Input Low Voltage
V
V
V
M a x
5.5
6.0
0.8
T yp
5.0
-
-
M in
4.5
2.4
-1.0
Note: All voltage referred to V ss.
T he supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr 01
CC
= 5V+/-10%, V ss
A
= 0 ~ 70C)
Symbol
Parameter
Note
V
OH
V
O L
Output Level
Output "H" Level Voltage (I
O U T
=
-5mA
)
Unit
V
V
M a x
V
C C
0.4
M in
2.4
0
Output Level
Output "L" Level Voltage (I
O U T
=
4.
2mA)
I
C C 1
I
C C 2
mA
S tandby Current (TTL)
Power Supply Standby Current
(RAS, UCAS, LCAS = V
IH
,
D
O U T
=
High-Z)
2
-
I
C C 3
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
R C
=
t
R C
min)
I
C C 4
I
C C 5
mA
S tandby Current (CMOS)
Power Supply Standby Current
(RAS, UCAS or LCAS >= V
CC
- 0.2V, D
OUT
= High-Z)
1
-
I
C C 6
CAS-before-RAS Refresh Current
(t
R C
=
t
R C
min)
150
-
I
L(I)
uA
10
-10
I
L(O)
uA
10
-10
Input Leakage Current
Any Input (0V
<=
V
IN
<=
6V)
Output Leakage Current
(D
O U T
is Disabled, 0V
<=
V
O U T
<=
6V)
Fast Page Mode Current
Fast Page Mode
(
PC
= t
PC
min)
mA
110
50ns
ns
70
100
90
1, 2
-
2
mA
-
110
50ns
ns
70
100
90
-
115
50ns
ns
70
105
95
mA
110
50ns
ns
70
-
-
90
I
C C 8
(Standby with CBR Refresh)
(
=31.3us
,
<=
0.3
O U T
=
500
-
uA
I
C C 9
uA
(RAS, UCAS or LCAS<=0.2V
O U T
=
300
-
Note: 1. I
C C
depends on output load condition when the device is selected.
(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = V
I L
3. Address can be changed once or less while LCAS and UCAS = V
IH
.
5. L-version.
Operating Current
(RAS, UCAS or LCAS Cycling
:
t
R C
=
t
R C
min)
mA
-
1
U
CAS, LCAS = V
D
O U T
5
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr'01
Capacitance
(V
CC
= 5V+/-10%, T
A
= 25C)
Symbol
Parameter
Note
C
I1
C
I2
C
I/O
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
1
1
1, 2
Unit
pF
pF
pF
M a x
5
7
7
M in
-
-
-
AC Characteristics
(V
CC
= 5V+/-10%, T
A
= 0 ~
+
70C, Vss = 0V, Note 1, 2, 3, 19)
Test Conditions
Input rise and fall times : 5 ns
Output timing reference levels : 0.4V, 2.4V
Input timing reference levels : 0.8V , 2.4V
Output load : 2TTL gate + C
L
(100 pF)
(Including scope and jig)
Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method.
2. UCAS and LCAS = V
IH
to disable D
O U T
.
R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles
(Common Parameters)
Symbol
Parameter
Note
Max
Unit
Min
Max
Min
Max
Min
t
R C
Random Read or Write Cycle Time
9 0
-
110
-
130
-
t
R P
30
-
40
-
50
-
t
R A S
50
10,000
60
10,000
70
10,000
t
C A S
10,000
10,000
10,000
15
18
t
A S R
Row Address Set up Time
0
-
-
-
0
0
t
R A H
Row Address Hold Time
7
-
-
-
10
10
t
A S C
Column Address Set-up Time
0
-
-
-
0
0
t
CAH
Column Address Hold Time
-
-
-
10
15
t
R C D
17
45
45
52
20
20
4
t
R A D
12
30
30
35
15
15
5
t
R S H
RAS Hold Time
13
-
-
-
15
18
t
CSH
50
-
-
-
60
70
t
C R P
5
-
-
-
5
5
t
T
T ransition Time (Rise and Fall)
3
50
50
50
3
3
8
R A S Precharge Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS Hold Time
CAS to RAS Precharge Time
t
DZO
0
-
-
-
0
0
t
DZC
0
-
-
-
0
0
OE Delay Time from D
IN
CAS Delay Time from D
IN
G M 7 1 C ( S ) 1 6 1 6 0
C / C L - 5
13
-
-
-
15
18
6
OE to D
IN
Delay Time
7
7
t
CP
7
-
10
-
10
-
C A S Precharge Time
t
O D D
G M 7 1 C ( S ) 1 6 1 6 0
C / C L - 6
G M 7 1 C ( S ) 1 6 1 6 0
C / C L - 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
7
25
22
22
23
RAS Pulse Width
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