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Datasheet: GM71C17400CLT-7 (Hynix Semiconductor)

4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM

 

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Hynix Semiconductor
GM71C(S)17400C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
The GM71C(S)17400C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17400C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17400C/CL
offers Fast Page Mode as a high speed access
mode. Multiplexed address inputs permit the
GM71C(S)17400C/CL to be packaged in a
standard 300 mil 24(26) pin SOJ, and a standard
300 mil 24(26) pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
System oriented features include single power
supply 5.0V+/-10% tolerance, direct interfacing
capability with high performance logic families
such as Schottky TTL.
Features
* 4,194,304 Words x 4 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5.0V+/-10%)
* Fast Access Time & Cycle Time
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery backup operation (L-version)
* Test function : 16bit parallel test mode
(Unit: ns)
GM71C(S)17400C/CL-5
GM71C(S)17400C/CL-6
GM71C(S)17400C/CL-7
t
RAC
t
CAC
t
RC
t
PC
50
60
13
15
90
110
35
40
70
18
130
45
Pin Configuration
24(26) SOJ
(Top View)
V
CC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
24(26) TSOP II
V
CC
I/O1
I/O2
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
Rev 0.1 / Apr'01
GM71C(S)17400C/CL
Rev 0.1 / Apr'01
Pin Description
Pin
Function
Pin
Function
A0-A10
A0-A10
I/O1-I/O4
V
CC
V
SS
Address Inputs
Refresh Address Inputs
Data Input/Data Output
Row Address Strobe
Column Address Strobe
Read/Write Enable
Output Enable
Power (5.0V)
Ground
Ordering Information
Type No.
Access Time
Package
GM71C(S)17400CJ/CLJ-5
GM71C(S)17400CJ/CLJ-6
GM71C(S)17400CJ/CLJ-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic SOJ
GM71C(S)17400CT/CLT-5
GM71C(S)17400CT/CLT-6
GM71C(S)17400CT/CLT-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Note: All voltage referred to Vss.
RAS
CAS
Recommended DC Operating Conditions (T
A
= 0 ~ 70C)
OE
NC
No Connection
WE
Symbol
Parameter
Rating
Unit
T
A
T
STG
V
IN
/V
OUT
V
CC
I
OUT
0 ~ 70
-55 ~ 125
-1.0 ~ 7.0
-1.0 ~ 7.0
50
Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to V
SS
Voltage on V
CC
Relative to V
SS
Short Circuit Output Current
V
V
mA
P
D
1.0
Power Dissipation
W
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
C
C
Symbol
Parameter
Unit
V
CC
V
IH
V
IL
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
Max
5.5
6.0
0.8
Typ
5.0
-
-
Min
4.5
2.4
-1.0
GM71C(S)17400C/CL
Rev 0.1 / Apr'01
DC Electrical Characteristics (V
CC
= 5.0V+/-10%, Vss = 0V, T
A
= 0 ~ 70C)
Symbol
Parameter
Note
V
OH
V
OL
Output Level
Output "H" Level Voltage (I
OUT
=
-5mA
)
Unit
Max
V
CC
0.4
Min
2.4
0
Output Level
Output "L" Level Voltage (I
OUT
=
4.2
mA)
I
CC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling
:
t
RC
=
t
RC
min)
I
CC2
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = V
IH
,
D
OUT
=
High-Z)
I
CC3
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
RC
=
t
RC
min)
I
CC4
I
CC5
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= V
CC
- 0.2V, D
OUT
= High-Z)
1
-
I
CC6
CAS-before-RAS Refresh Current
(t
RC
=
t
RC
min)
150
-
I
CC8
I
L(I)
10
-10
I
L(O)
10
-10
Input Leakage Current
Any Input (0V
<=
V
IN
<=
6V)
Output Leakage Current
(D
OUT
is Disabled, 0V
<=
V
OUT
<= 6
V)
Note: 1. I
CC
depends on output load condition when the device is selected.
I
CC
(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = V
IL
.
3. Address can be changed once or less while CAS = V
IH
.
4. L-version.
Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
(t
PC
= t
PC
min)
2
-
100
-
50ns
60ns
70ns
90
80
-
-
-
100
-
50ns
60ns
70ns
90
80
-
-
90
-
50ns
60ns
70ns
80
70
-
V
V
mA
uA
uA
I
CC7
-
5
Standby Current RAS = V
IH
CAS = V
IL
D
OUT
=
Enable
1
mA
Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, t
RC
=62.5us
,
t
RAS
<=
0.3
us,
D
OUT
=
High-Z, CMOS interface)
350
-
uA
4
uA
4
mA
mA
1, 2
mA
2
mA
1, 3
mA
-
100
-
50ns
60ns
70ns
90
80
-
GM71C(S)17400C/CL
Rev 0.1 / Apr'01
Capacitance (V
CC
= 5.0V+/-10%, T
A
= 25C)
AC Characteristics (V
CC
= 5.0V+/-10%, Vss=0V, T
A
= 0 ~ 70C, Notes 1, 2, 18,19)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
Note
C
I1
C
I2
C
I/O
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
1
1
1, 2
Unit
pF
pF
pF
Max
5
7
7
Min
-
-
-
Input rise and fall times : 5ns
Input timing reference levels : 0.8V, 2.4V
Output timing reference levels : 0.4V, 2.4V
Output load : 2 TTL gate + C
L
(100pF)
(Including scope and jig)
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = V
IH
to disable D
OUT
.
Test Conditions
Symbol
Parameter
Note
Max
Unit
Min
Max
Min
Max
Min
t
RC
90
-
110
-
130
-
t
RP
30
-
40
-
50
-
t
RAS
50
10,000
60
10,000
70
10,000
t
CAS
10,000
10,000
10,000
15
18
t
ASR
0
-
-
-
0
0
t
RAH
7
-
-
-
10
10
t
ASC
0
-
-
-
0
0
t
CAH
-
-
-
10
15
t
RCD
17
45
45
52
20
20
3
t
RAD
12
30
30
35
15
15
4
t
RSH
13
-
-
-
15
18
t
CSH
50
-
-
-
60
70
t
CRP
5
-
-
-
5
5
t
T
3
50
50
50
3
3
7
t
DZO
0
-
-
-
0
0
t
DZC
0
-
-
-
0
0
GM71C(S)17400
C/CL-5
13
-
-
-
15
18
5
6
6
t
CP
-
10
-
10
-
t
ODD
GM71C(S)17400
C/CL-6
GM71C(S)17400
C/CL-7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
7
7
Random Read or Write Cycle Time
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS Hold Time
Transition Time (Rise and Fall)
RAS Precharge Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS Hold Time
CAS to RAS Precharge Time
OE Delay Time from D
IN
CAS Delay Time from D
IN
OE to D
IN
Delay Time
CAS Precharge Time
RAS Pulse Width
CAS Pulse Width
GM71C(S)17400C/CL
Rev 0.1 / Apr'01
Read Cycle
Write Cycle
Symbol
Parameter
Max
Min
Max
Min
-
60
-
70
-
15
-
18
-
30
-
35
0
-
0
-
0
-
-
0
5
-
-
5
30
-
-
35
0
-
-
0
30
-
-
35
-
15
15
-
-
15
-
18
3
-
-
3
3
-
-
3
-
15
15
-
15
-
-
18
Access Time from Address
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Access Time from RAS
Access Time from CAS
CAS to Output in low-Z
Column Address to CAS Lead Time
Output Buffer Turn-off Time
Access Time from OE
Output Data Hold Time
Output Data Hold Time from OE
Output Buffer Turn-off Time to OE
CAS to D
IN
Delay Time
GM71C(S)17400
C/CL-6
GM71C(S)17400
C/CL-7
Max
Min
-
50
-
13
-
25
0
-
0
-
5
-
25
-
0
-
25
-
-
13
-
13
3
-
3
-
-
13
13
-
GM71C(S)17400
C/CL-5
Symbol
Parameter
Max
Min
Max
Min
0
-
0
-
10
-
15
-
10
-
10
-
15
-
18
-
15
-
-
18
0
-
-
0
t
RAC
t
CAC
t
AA
t
RCS
t
RCH
t
RRH
t
RAL
t
CLZ
t
CAL
t
OFF
t
OAC
t
OH
t
OHO
t
OEZ
t
CDD
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Data-in Setup Time
Data-in Hold Time
10
-
-
15
Write Command to RAS Lead Time
Write Command to CAS Lead Time
GM71C(S)17400
C/CL-6
GM71C(S)17400
C/CL-7
Min
0
-
-
7
-
-
-
0
-
-
Max
GM71C(S)17400
C/CL-5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
7
13
13
7
Note
12
12
8,9,20
9,11,
17,20
9,10,
17,20
13
9
13
5
15
15
14
Note
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