HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: GM0936TQ (Hynix Semiconductor)

Voice-band Audio Codec For Cdma

 

Скачать: PDF   ZIP
Hynix Semiconductor
GM0936TQ
1
Features
Designed for standard 2.048MHz master
clock for U.S. Analog, U.S. Digital, CT2,
DECT, GSM, and PCS Standards for
Hand-held Battery-Powered Telephones
On-chip voltage references
Package Type : 48 LQFP, 20 DIP, 20 SOP
Single 3-V operation
Low power consumption
Operating mode .... 20mW Typ
Power-down mode ... 1mW Typ
Combined A/D, D/A, and Filters
Electret microphone bias reference
voltage available
Compatible with all digital signal
processors (DSPs)
Programmable volume control
300 Hz - 3.6 kHz Passband with Specified
Master clock
NC
NC
NC
AVcc
NC
NC
NC
NC
DVcc
NC
__________
MICMUTE
NC
VMID
NC
AGND
NC
NC
NC
NC
NC
NC
DGND
NC
NC
1
2
3
5
6
7
8
9
10
11
12
4
36
35
34
32
31
30
29
28
26
25
33
27
48
47
46
44
43
42
41
40
38
37
45
39
13
14
15
17
18
19
20
21
23
24
16
22
NC
NC
EARGS
EARB
EARA
____
PDN
MICBIAS
MICGS
MICIN
EXTMIC
MICSEL
NC
NC
NC
DIN
FSR
__________
EARMUTE
NC
CLK
FSX
DOUT
NC
NC
NC
48 LQFP
(TOP VIEW)
____
PDN
EARA
EARB
EARGS
Vcc
__________
MICMUTE
NC
DIN
FSR
__________
EARMUTE
MICBIAS
MICGS
MICIN
VMID
GND
NC
NC
DOUT
FSX
CLK
1
2
3
5
6
7
8
9
10
4
20
19
18
16
15
14
13
12
17
11
20 DIP/SOP
(TOP VIEW)
GM0936TQ
Voice-Band Audio CODEC for CDMA
GM0936TQ
2
Description
The GM0936TQ contains A/D and D/A conversion functions integrated on a single chip, and utilizes
the sigma-delta modulation technique to achieve high resolution data conversion and low power
consumption. The GM0936TQ is an ideal analog front end device for high performance voice-band
communication systems. Cellular telephone systems are targeted in particular; however, these
integrated circuits can function in other systems including digital audio, telecommunications, and data
acquisition.
The transmit section is designed to interface directly with an electret microphone element. One of two
microphone input signals, MICIN and EXTMIC, is selected by MICSEL. If MICSEL is floated or
Low, then MICIN is selected, and if MICSEL is high, then EXTMIC is selected. The microphone input
signal (MICIN and EXTMIC) is buffered, first-order low-pass filtered, and amplified with provision for
setting the amplifier gain to accommodate a range of signal input levels. The amplified signal is 1bit-
modulated by second-order sigma-delta modulator. The modulated signal is then applied to the input of
high-performance FIR-type digital decimation filters with frequency response equalization. The
resulting data is then clocked out of DOUT as a serial data stream.
The receive section takes a frame of sereal data on DIN and converts it to analog through high-
performance FIR-type digital interpolation filter together with frequency response equalization,
second-order digital sigma-delta modulator, and analog reconstruction filters.
On-chip voltage reference ensures a highly integrated solution and all internal voltage references are
generated. An internal reference voltage, VMID, is used to develop the midlevel virtual ground for all
the amplifier circuits and the microphone bias circuit.Another reference voltage, MICBIAS, can supply
bias current for the microphone.
Serial DSP interfaces for transmit and receive paths support directly industry standard DSP processors.
The GM0936TQ devices are characterized for operation from -20 to 70
.
GM0936TQ
3
Block Diagram
Analog 2nd order
-
Modulator Block Diagram
Integrator1
Integrator2
Quantizer
1/2
1/2
Y
x
Digital 2nd order
-
Modulator Block Diagram
Quantizer
2
Y
x
Delay1
Delay2
ANALOG
-MODULATOR
VOLTAGE
REFERENCE
POST
FILTER
1-BIT
DAC
SINC 3-
FILTER
FIR-
FILTER
DIGITAL
-
MODULATOR
SINC 2-
FILTER
FIR-
FILTER
VMID
MICIN
AV
CC
AGND
DV
CC
DGND
INTERFACE
DIN
DOUT
CLK
MICMUTE
EARA
EARB
MICGS
MICBIAS
FSR
FSX
MICSEL
EXTMIC
EARGS
__________
EARMUTE
_ __
PDN
GM0936TQ
4
Pin Description
ANALOG SIGNALS
TERMINAL
NAME
LQFP
SOP&DIP
I/O
DESCRIPTION
AGND
34
16
Analog Ground
AVcc
4
5
Analog Power (3V)
EARA
44
2
O
Earphone output
EARB
45
3
O
Side-tone output
EARGS
46
4
I
Side-tone input
EARMUTE_
17
10
I
Earphone output mute control signal
MICBIAS
42
20
O
Microphone bias
MICGS
41
19
O
Output of the internal microphone amplifier
MICIN
40
18
I
Microphone input
MICMUTE_
11
6
I
Microphone input mute
VMID
36
17
O
Bias voltage reference. A pair of external, low-
leakage, high-frequency capacitors (1
F and
470 pF) should be connected between VMID
and ground for filtering
ETMIC
39
N/A
I
Hand-free MIC-IN
MICSEL
38
N/A
I
MIC-IN selection input. When float or
low, MICSEL selects MICIN. When high,
MICSEL selects EXTMIC.
GM0936TQ
5
Pin Description
DIGITAL SIGNALS
TERMINAL
NAME
LQFP
SOP&DIP
I/O
DESCRIPTION
CLK
19
11
I
Clock input (2.048 MHz)
DGND
27
16
Digital ground
DIN
15
8
I
Receive data input
DOUT
21
13
O
Transmit data output
DVcc
9
5
Digital power (3 V)
FSR
16
9
I
Frame-synchronization clock input for
receive channel
FSX
20
12
I
Frame-synchronization clock input for
receive channel
PDN_
43
1
I
Power-down input, Active Low
NC
1,2,3,
5,6,7,
8,10,
12,13,
14,18,
22,23,
24,25,
26,28,
29,30,
31,32,
33,35
7, 14, 15
No internal connection
GM0936TQ
6
Electrical Characteristics
SYMBOL
PARAMETER
MIN
MAX
UNIT
DV
CC
, AV
CC
Supply Voltage Range
V
V
ind
Digital Input Voltage Range
- 0.3
V
V
ina
Analog Input Voltage Range
- 0.3
V
Absolute Maximum Ratings over operating free-air temperature range
TYP
SYMBOL
PARAMETER
MIN
MAX
UNIT
DV
CC
, AV
CC
Supply Voltage
3.3
V
V
IH
High-level Input Voltage
V
T
A
Operating free-air
Temperature
-20
70
Recommended Operating Conditions
TYP
3.0
2.7
0.8
- 0.3
3.6
3.6
3.6
Low-level Input Voltage
V
IL
2.2
V
PARAMETER
MIN
MAX
UNIT
Power Dissipation , Operating
mW
Power Dissipation , Power down
TYP
Power Supply Characteristics,
f
CLK
= 2.048 MHz, outputs not loaded, Vcc=3V, T
A
=25
18
1
mW
PARAMETER
MIN
MAX
UNIT
Input Capacitance
10
pF
Input Leakage Current
- 10
10
Low-level output Voltage (I
OL
= 3.2mA)
0.4
V
High-level output Voltage (I
OH
= -3.2mA)
2.4
V
TYP
Digital Characteristics
(T
A
=25 , DV
CC
= AV
CC
= 3V)
GM0936TQ
7
TEST CONDITIONS
PARAMETER
MIN
MAX UNIT
V
I
= 0 to 3 V
V
IO
Input offset voltage at MICIN
mV
nA
MHz
Microphone interface
TYP
Speaker interface
+5
+200
1.5
I
IB
Input bias current at MICIN
B
1
Unity-gain bandwidth, open loop at MICIN
V/V
A
10000
3
Av Large-signal voltage amplification at MICGS
VMID
mA
1
MICBIAS(source only)
Iomax Maximum
output current
TEST CONDITIONS
PARAMETER
MIN
MAX UNIT
V
O(PP)
AC output voltage
Vpp
mA
TYP
3
+1
1
I
Omax
Maximum output current
r
o
Output resistance at EARA, EARB
dB
-60
Gain change
R
L
= 600
EARMUTE low, max level
when muted
GM0936TQ
8
PARAMETER
MIN
MAX
UNIT
Oversampling Ratio
128
Resolution
13
bit
Dynamic Range
dB
S/(N+THD)
dB
Analog Characteristics
(T
A
=25 , DV
CC
= AV
CC
= 3V, fs = 8 KHz)
TYP
A/D Converter
70
50
Output Sample Rate
8
KHz
Maximum output current for MICBIAS
1
mA
Maximum output voltage for Microphone
Amplifier
Vpp
0.95
PARAMETER
MIN
MAX UNIT
0.76
0.73
dB
TYP
Transmit filter transfer over recommended ranges of supply voltage and free-air
temperature, CLK=2.048 MHz, FSX=8 kHz
0.67
0
-1.9
-4.5
Gain relative to
input signal at
1.02 kHz
Input amplifier set for
unity gain, the output for
400mVpp signal at
MICGS is 0dB
f
MICIN
= 50 Hz
f
MICIN
= 200 Hz
f
MICIN
= 300 Hz
f
MICIN
= 1 kHz
f
MICIN
= 2 kHz
f
MICIN
= 3 kHz
TEST CONDITIONS
-5.4
-8.9
f
MICIN
= 3.3 kHz
f
MICIN
= 3.8 kHz
52
0.85
GM0936TQ
9
PARAMETER
MIN
MAX
UNIT
Oversampling Ratio
Resolution
13
bit
Dynamic Range
dB
S/(N+THD)
dB
TYP
D/A Converter
128
67
54
Maximum output current (R
L
=600
)
mA
Output Voltage Range
Vpp
0.81
+ 1
0.91
PARAMETER
MIN
MAX UNIT
178
53
dB
TYP
Transmit idle channel noise and distortion, linear mode selected, over recommended
ranges of supply voltage and free-air temperature (see Notes 1 and 2)
52.3
51.9
50.7
49.0
Gain relative to
input signal at
1.02 kHz
MICIN connected to MICGS through a 22 k
resistor
MICIN to DOUT at 0 dBm0
TEST CONDITIONS
V
rms
Transmit noise
MICIN to DOUT at -3 dBm0
MICIN to DOUT at -6 dBm0
MICIN to DOUT at -9 dBm0
MICIN to DOUT at -12 dBm0
Notes: 1. The input amplifier is set for inverting unity gain.
2. Transmit noise, linear mode: 200
V
rms
is equivalent to -75 dB (referenced to device 0 dB level).
PARAMETER
MIN
MAX UNIT
60
59.7
dB
TYP
Receive distortion, linear mode selected, over recommended
ranges of supply voltage and free-air temperature
59.6
56.1
55.3
Receive signal-to
-distortion ratio
with sine-wave
input
DIN to EARA at -3 dBm0
TEST CONDITIONS
DIN to EARA at -6 dBm0
DIN to EARA at -9 dBm0
DIN to EARA at -12 dBm0
DIN to EARA at 0 dBm0
48
GM0936TQ
10
PARAMETER
MIN
MAX UNIT
Supply voltage rejection,
transmit channel
dB
Supply voltage rejection,
receive channel
TYP
Power supply rejection over recommended ranges of supply voltage and operating
free-air temperature
-50
TEST CONDITIONS
Idle channel, supply signal = 100mVrms
f = 1 kHz (measured at DOUT)
Idle channel, supply signal = 100mVrms
f = 1 kHz (measured at EARA)
dB
-50
GM0936TQ
11
Transmit timing requirements
Receive timing requirements
MIN MAX
UNIT
t
su
(FSX) Setup time, FSX high before CLK
t
h
(FSX) Hold time, FSX high after CLK
20 468
20 468
ns
ns
MIN MAX
UNIT
t
su
(FSR) Setup time, FSR high before CLK
t
h
(FSR) Hold time, FSR high after CLK
20 468
20 468
ns
ns
t
su
(DIN) Setup time, DIN high or low before CLK
t
h
(DIN) Hold time, DIN high or low after CLK
20
20
ns
ns
Clock timing requirements
MIN NOM MAX
UNIT
Duty cycle, CLK
45% 50% 55%
PARAMETER
MIN
MAX
UNIT
CLK Frequency
Sampling Rate
8
KHz
DIN Delay from CLK
ns
DOUT Delay from CLK
ns
TYP
35
Timing
(T
A
=25 , DV
CC
= AV
CC
= 3V)
2.048
MHz
35
GM0936TQ
12
CLK
FSR
1
2
Figure1. Receive Side Timing Diagram
Timing Diagram
0 1 2 3 4
15 16 17
See Note B
See Note A
t
h
(FSR)
t
su
(FSR)
20%
80%
Receive Time Slot
80%
3
DIN
15
16
15
16
1
4
t
h
(DIN)
t
su
(DIN)
20%
CLK
FSX
Figure2. Transmit Side Timing Diagram
0 1 2 3 4
15 16 17
See Note B
See Note A
t
h
(FSX)
t
su
(FSX)
20%
80%
Transmit Time Slot
80%
DOUT
t
pd3
20%
NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low.
C. Transitions are measured at 50%.
t
pd1
See Note C
See Note C
t
pd2
1
2
3
4
15
16
GM0936TQ
13
PRINCIPLES OF OPERATION
power-down operation
To minimize power consumption, a power-down mode is provided.
For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is
internally pulled up to a high logic level and the device remains active. In the power-down
mode, the average power consumption is reduced to 1mW.
Timing
FSX and FSR are inputs that set the sampling frequency. Data is transmitted on DOUT on the
positive transitions of CLK following the rising edge of FSX. Data is received on DIN on the
falling edges of CLK following FSR.
DEVICE STATUS
Power on
Power down
PROCEDURE
PDN =high,
FSX = pulses,
FSR = pulses
PDN =low,
FSX,FSR =X
TYPICAL POWER
CONSUMPTION
20 mW
1 mW
DIGITAL OUTPUT STATUS
Digital outputs active
DOUT in the high-impedance state
Table 1. Power-On and Power-Down Procedures
X = dont care
GM0936TQ
14
Reference
Voltage
Generator
To 2nd-order
-
Modulator
Microphone Amplifier
VMID Reference
For Amplifiers
MICBIAS
MICGS
MICIN
40
41
42
VMID
36
4.4
F
470 pF
GM0936TQ
100nF
Electret
Microphone
22 k
2 k
22 k
2.2 nF
NOTE A: Terminal numbers shown are for the 48 LQFP package.
transmit operation
The microphone input amplifier is designed specifically to interface to electret-type microphone
elements, as shown in Figure 3. The VMID buffer circuit provides a voltage (MICBIAS) as a bias
voltage to the electret microphone. The microphone amplifier output (MICGS) is used in conjunction
with a feedback network and applied to the amplifier inverting input (MICIN) to set the amplifier gain.
VMID appears at a terminal to provide a place to filter the VMID voltage.
microphone input
Figure 3. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT.
transmit filter
A low-pass antialiasing section is implemented by connecting a RC-pair externally between MICGS
and MICIN. The RC-pair, together with the microphone amplifier, provides a single-pole low pass
filter. The antialiased signal is 1bit-modulated by second-order sigma-delta modulator. The modulated
signal is then applied to the input of high-performance FIR-type digital decimation filters with
frequency response equalization.
PRINCIPLES OF OPERATION
GM0936TQ
15
encoding
The encoder performs an A/D conversion on a 2nd-order Sigma-Delta (
-
) modulator using a
switched-capacitor technology and high-performance FIR-type digital decimation filters with
frequency response equalization. The resulting data is then clocked out of DOUT as a serial data.
data word structure
The data word is 16 bits long. The first 13 bits comprises the audio data sample, and the last three bits
form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit
direction (DOUT). The sign bit is transmitted first.
receive operation
decoding
The serial data word is received at DIN on the first 13 clock cycles. The receive section converts a
frame of sereal data to analog through high-performance FIR-type digital interpolation filter together
with frequency response equalization, second-order digital sigma-delta modulator, and analog
reconstruction filters.
receive buffer
The receive buffer contains the volume control.
earphone amplifier
The output can be used to drive a single-ended load with the output signal voltage centered around
VMID. EARA in Figure 4 is the output pin for the decoded analog signal. EARB in the figure is used
for sidetone signal output which is used internally. A resistor-capacitor pair attached to EARB is
embedded to reduce the number of on-board components. See the next section for more information on
sidetone generation.
PRINCIPLES OF OPERATION
GM0936TQ
16
NOTE A: Terminal numbers shown are for the 48 LQFP package.
EARB
45
GM0936TQ
EARGS
46
100 k
40 pF
VMID
VMID
EARA
44
40 pF
40 pF
30 k
30 k
50 k
50 k
Figure 4. Earphone Audio-Output Amplifier Configuration
PRINCIPLES OF OPERATION
receive data format
In the decoding operation, 16 bits of data are received. The first 13 bits are the D/A code, and the
remaining three bits from the volume control word(see Table 2). The volume control function is
actually an attenuation control in which the first bit received is the most significant. The maximum
volume occurs when all three volume control bits are zero. Eight levels of attenuation are selectable in
3-dB steps, giving a maximum attenuation of 21 dB when all bits are 1s. The volume control bit are not
latched into the GM0936TQ and must be present in each received data word.
GM0936TQ
17
BIT NO. Data
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V2
V1
V0
0
D12
Table 2. Receive-Data Bit Definitions
MSB
(sign bit)
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 V2 V1 V0
LSB
PCM Data
Volume Control
Time
Where:
D12-D0 = PCM Data word
V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 0 dB
111 = minimum volume, -21 dB
GM0936TQ
18
NOTE A: Terminal numbers shown are for the 48 TQFP package.
higher clock frequencies and sample rates
The GM0936TQ is designed to work with sample rates up to 16kHz where the frequency of the frame
sync determines the sampling frequency. However, there is a fundamental requirement to maintain the
ratio of the master clock frequency, f
CLK
, to the frame sync frequency, f
FSR
/ f
FSX
. This ratio for the
GM0936TQ is 2.048 MHz/8 kHz, or 256 master clocks per frame sync. For example, to operate the
GM0936TQ at a sampling rate of f
FSR
and f
FSX
equal to 16 kHz, f
CLK
must be 256 times 16 kHz, or
4.096 MHz. If the GM0936TQ is operated above an 8-kHz sample rate, however, it is expected that the
performance becomes somewhat degraded. Exact parameter specifications for rates up to 16-kHz
sample rate are not specified at this time.
output gain set and sidetone considerations
The single-ended outputs EARA and EARB are capable of driving output power level up to 1mW into
load impedance of 1k
separately.The sidetone signal and the received signal can be summed by
configuring external components like in Figure 5. The amount of sidetone mixing is controlled by the
resistor connected between EARB and EARGS. If the resistance become greater, the amount of
sidetone mixing increases.
Figure 5. Configuration for Gain-Setting and Sidetone
EARB
MICGS
MICIN
40
41
42
100nF
Electret
Microphone
22 k
22 k
2.2 nF
EARGS
46
EARA
44
100 k
1 k
GM0936TQ
APPLICATION INFORMATION
To speaker driving amp.
GM0936TQ
19
GM0936TQ
20
GM0936TQ
21
© 2018 • ChipFind
Контакты
Главная страница