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Datasheet: GDC21D003 (Hynix Semiconductor)

Vsb Receiver

 

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Hynix Semiconductor
GDC21D003
(VSB Receiver)
Version 1.0
Mar, 99
HDS-GDC21D003-9908 / 10
3
GDC21D003
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or
patent rights of Hyundai or others.
These Hyundai products are intended for usage in general electronic equipment (office equipment,
communication equipment, measuring equipment, domestic electrification, etc.).
Please make sure that you consult with us before you use these Hyundai products in equipment which
require high quality and / or reliability, and in equipment which could have major impact to the welfare of
human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of
safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these
Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.
Copyright 1999 Hyundai Micro Electronics Co.,Ltd.
All Rights Reserved
4
GDC21D003
TABLE OF CONTENTS
1. General Description................................................................................................................. 8
2. Features .................................................................................................................................... 8
3. Internal Block Diagram.......................................................................................................... 11
4. Pin Description....................................................................................................................... 11
4.1 Pin Configuration .............................................................................................................. 11
4.2 Pin Description.................................................................................................................. 14
4.3 Pin Assignment ................................................................................................................. 16
5. I
2
C Bus I/F & Registers .......................................................................................................... 17
5.1 I
2
C Bus I/F Description...................................................................................................... 17
5.1.1 Write Operation ........................................................................................................... 17
5.1.2 Read Operation ........................................................................................................... 17
5.2 I
2
C Bus Register Configuration ......................................................................................... 18
5.3 I
2
C Bus Register Description ............................................................................................ 20
6. Functional Description .......................................................................................................... 29
6.1 ADC .................................................................................................................................. 29
6.1.1 Electrical Characteristics............................................................................................. 30
6.1.2 Timing Diagram ........................................................................................................... 32
6.1.3 Application Circuits...................................................................................................... 33
6.2 Clock Divider..................................................................................................................... 35
6.3 Synchronizer ..................................................................................................................... 36
6.3.1 Input Control................................................................................................................ 36
6.3.2 DC Reduction .............................................................................................................. 39
6.3.3 Auto Gain Control(AGC) ............................................................................................. 39
6.3.4 Polarity Correction....................................................................................................... 40
6.3.5 Data Segment Sync Recovery .................................................................................... 41
6.3.6 Polarity Decision.......................................................................................................... 42
6.3.7 Timing Recovery ......................................................................................................... 43
6.3.8 Field Sync Recovery ................................................................................................... 46
6.3.9 VSB Mode Detect........................................................................................................ 47
6.3.10 NTSC Rejection......................................................................................................... 48
6.4 Equalizer ........................................................................................................................... 50
6.4.1 Block Diagram ............................................................................................................. 50
6.4.2 Training/Data Mode Equalization ................................................................................ 51
6.4.3 Error Estimation........................................................................................................... 52
6.4.4 Adaptive Filter ............................................................................................................. 53
6.4.5 Equalizer Clock Scheme ............................................................................................. 53
6.4.6 I
2
C Bus I/F ................................................................................................................... 54
6.4.7 Coefficient Reading/Writing......................................................................................... 56
5
GDC21D003
6.5 Phase Tracker .................................................................................................................. 56
6.5.1 Error Detection ............................................................................................................ 57
6.5.2 Gain & Offset Loop...................................................................................................... 58
6.5.3 Phase Loop ................................................................................................................. 58
6.5.4 I2C Bus I/F .................................................................................................................. 59
6.6 Channel Decoder .............................................................................................................. 60
6.6.1 12 Symbol Intrasegment Deinterleaver....................................................................... 61
6.6.2 Segment Sync Suspension ......................................................................................... 61
6.6.3 Viterbi Decoder............................................................................................................ 62
6.6.4 Symbol-to-Byte Converter........................................................................................... 64
6.6.5 Convolutional Deinterleaver ........................................................................................ 65
6.6.6 Reed-Solomon Decoder.............................................................................................. 65
6.6.7 Data Derandomizer ..................................................................................................... 66
6.6.8 I/F to Transport Demultiplexer..................................................................................... 67
6.7 PLL.................................................................................................................................... 74
7. Electrical Characteristics ...................................................................................................... 75
8. Package Dimensions ............................................................................................................. 77
9. Application Notes .................................................................................................................. 78
Figures
Figure 3.1 Functional Block Diagram .............................................................................. 10
Figure 5.1.1 I
2
C Write Operation Example .......................................................................... 17
Figure 5.1.2 I
2
C Read Operation Example .......................................................................... 18
Figure 6.1.1 The Block Diagram of ADC ............................................................................. 29
Figure 6.1.2 Timing Diagram of ADC .................................................................................. 32
Figure 6.1.3 ADC Application Circuit ................................................................................... 33
Figure 6.1.4 Equivalent Circuits .......................................................................................... 34
Figure 6.3.1 The Block Diagram of Input Selection ............................................................ 36
Figure 6.3.2 Digital Input Setting Up & Chip I/F Circuit(1) .................................................. 37
Figure 6.3.3 Digital Input Setting Up & Chip I/F Circuit(2) .................................................. 38
Figure 6.3.4 The Block Diagram of DC Reduction .............................................................. 39
Figure 6.3.5 The Block Diagram of AGC ............................................................................ 40
Figure 6.3.6 AGC Signal I/F for DTV System ..................................................................... 40
Figure 6.3.7 The Block Diagram of Polarity Correction ....................................................... 41
Figure 6.3.8 The Block Diagram of Data Segment Sync Recovery .................................... 41
Figure 6.3.9 Polarity signal I/F Circuit ................................................................................. 42
Figure 6.3.10 Timing Recovery Block .................................................................................... 43
Figure 6.3.11 Timing Recovery I/F Circuit(1) ......................................................................... 44
Figure 6.3.12 Timing Recovery I/F Circuit(2) ......................................................................... 45
Figure 6.3.13 Field Sync Structure ........................................................................................ 46
Figure 6.3.14 The Block Diagram of Field Sync Recovery .................................................... 46
Figure 6.3.15 Comb Filter Block ............................................................................................ 48
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GDC21D003
Figure 6.3.16 The Block Diagram of NTSC Rejection ............................................................ 49
Figure 6.4.1 Channel Equalizer ........................................................................................... 50
Figure 6.4.2 VSB Slicer ....................................................................................................... 51
Figure 6.4.3 Training/Data Equalization .............................................................................. 51
Figure 6.4.4 VSB Slice Level .............................................................................................. 52
Figure 6.4.5 Coefficient Update Filter ................................................................................. 53
Figure 6.4.6 I
2
C Bus I/F ....................................................................................................... 54
Figure 6.5.1 Phase Tracker ................................................................................................. 57
Figure 6.5.2 Error Detection ................................................................................................ 57
Figure 6.5.3 Coefficients of Hilbert Transform Filter ........................................................... 58
Figure 6.5.4 Complex Multiplier .......................................................................................... 58
Figure 6.6.1 Block Diagram of Channel Decoder ............................................................... 60
Figure 6.6.2 12-Symbol Intrasegment Deinterleaver .......................................................... 61
Figure 6.6.3 Segment Sync Suspension ............................................................................. 62
Figure 6.6.4 Viterbi Decoding with and without NTSC Rejection Filter ............................... 63
Figure 6.6.5 Internal Block Diagram of Viterbi Decoder ...................................................... 63
Figure 6.6.6 Convolutional Deinterleaver ............................................................................ 65
Figure 6.6.7 Derandomizer Polynomial ............................................................................... 66
Figure 6.6.8 I/F to Transport Demultiplexer when Register64[7:0] is set to
Default Value .................................................................................................... 68
Figure 6.6.9 I/F to Transport Demultiplexer when Register64[3] (Derand_on)
is set to ` 0' ........................................................................................................ 69
Figure 6.6.10 I/F to Transport Demultiplexer when Register64[2](Errorflg_ins)
is set to ` 0' ........................................................................................................ 69
Figure 6.6.11 I/F to Transport Demultiplexer when Register64[1](Vsbdvalid_pol)
is set to ` 0' ........................................................................................................ 70
Figure 6.6.12 I/F to Transport Demultiplexer when Register64[0](Vsbclk_sup)
is set to ` 0' ........................................................................................................ 70
Figure 6.6.13 I/F to Transport Demultiplexer(MMDS 8VSB Mode) ....................................... 71
Figure 6.6.14 I/F to Transport Demultiplexer at Serial Output Mode ..................................... 71
Figure 6.6.15 Connection with VSB Receiver and Transport Demultiplexer
Chip(GDC21D301A) ........................................................................................ 72
Figure 6.6.16 Connection with VSB Receiver and Transport Demultiplexer
Chip(L64007) ................................................................................................... 72
Figure 6.6.17 Connection with VSB Receiver and Transport Demultiplexer
Chip(AVIA-MAX) .............................................................................................. 73
Figure 6.7.1 Clock Scheme ................................................................................................. 74
Figure 7.1 Clock Reset Stabilization Timing ..................................................................... 76
Figure 7.2 Input and Output Timing .................................................................................. 76
Figure 8.1 Physical Dimensions ........................................................................................ 77
Figure 9.1 VSB Receiver Application Circuit ..................................................................... 78
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