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Datasheet: GLT441L08 (G-Link Technology Corp.)

 

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G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 1 -
Features :
Description :
524
,288 words by 8 bits organization.
Fast access time and cycle time.
Low power dissipation.
Read-Modify-Write, RAS -Only Refresh,
CAS -Before-RAS Refresh, Hidden
Refresh and Test Mode Capability.
1024
refresh cycles/16ms.
Available in 28-pin 400milSOJ/TSOP(II).
Single +3.3V
0.3V Power Supply.
All inputs and Outputs are TTL
compatible.
Fast Page Mode operation.
The GLT441L08 is a 524,288 x 8 bit
high-performance CMOS dynamic random
access memory. The GLT441L08 offers Fast
Page mode ,and has both BYTE WRITE and
WORD WRITE access cycles via two CAS
pins. The GLT441L08 has symmetric
address and accepts 1024-cycle refresh in
16ms interval.
All inputs are TTL compatible. Fast
Page Mode operation allows random access
up to 512 x 8 bits, within a page, with cycle
times as short as 40ns.
Pin Configuration :
28 Lead SOJ TSOP(TYPE II)
TOP VIEW TOP VIEW
V
cc
DQ
0
A9
A
0
A
1
A
2
A
3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
26
25
24
23
NC
A
8
A
7
V
SS
DQ
7
DQ
1
NC
V
CC
DQ
6
A
6
A
5
V
SS
14
27
28
DQ
5
DQ
4
CAS
OE
20
A
4
7
DQ
3
DQ
2
WE
RAS
V
cc
DQ
0
A9
A
0
A
1
A
2
A
3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
26
25
24
23
NC
A
8
A
7
V
SS
DQ
7
DQ
1
NC
V
CC
DQ
6
A
6
A
5
V
SS
14
27
28
DQ
5
DQ
4
CAS
OE
20
A
4
7
DQ
3
DQ
2
WE
RAS
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 2 -
HIGH PERFORMANCE
60
70
Max. RAS Access Time, (t
RAC
)
60 ns
70 ns
Max. Column Address Access Time, (t
AA
)
30 ns
35 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
40 ns
45 ns
Min. Read/Write Cycle Time, (t
RC
)
110 ns
130 ns
Max. CAS Access Time (t
CAC
)
15 ns
20 ns
Pin Descriptions:
Name
Function
A
0
A
9
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
DQ
0
- DQ
7
Data Inputs / Outputs
V
CC
3.3V Power Supply
V
SS
Ground
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 3 -
Absolute Maximum Ratings*
Capacitance*
T
A
=25
C, V
CC
=3.3V
0.3V, V
SS
=0V
Symbol
Parameter
Typ. Max. Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS
,
CAS
,
WE
,
OE
4
5
pF
Operating Temperature, T
A
(ambient)
.......................................0
C to +70
C
Storage Temperature(plastic)....-55
C to +150
C
Voltage Relative to V
SS
................-1.0V to + 4.6V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
C
OUT
Data Input/Output
5
7
pF
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
*Note:
Capacitance is sampled and not 100% tested
Electrical Specifications
l
All voltages are referenced to GND.
l
After power up, wait more than 200
s and then, execute eight
CAS
before
RAS
or
RAS
only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
1 0 2 4
O E
C L O C K
G E N E R A T O R
W E
C L O C K
G E N E R A T O R
C A S
C L O C K
G E N E R A T O R
R A S
C L O C K
G E N E R A T O R
D a t a I / O B U S
C O L U M N D E C O D E R S
S E N S E A M P L I F I E R S
I / O
B U F F E R
M E M O R Y
A R R A Y
R E F R E S H
C O U N T E R
.
.
X
0
- x
9
5 1 2 8
Y
0
- Y
8
9
I / O 0
I / O 1
I / O 2
I / O 3
I / O 4
I / O 5
I / O 6
I / O 7
O E
W E
R A S
C A S
V
C C
V
S S
A
0
A
1
A
8
A
9
A D D R E S S B U F F E R S
A N D P R E D E C O D E R S
R O W
D E C O D E R S
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 4 -
Truth Table: GLT441L08
Function
RAS
CAS
WE
OE
ADDRESS
DQs
Notes
Standby
H
H
X
X
X
High-Z
Read
L
L
H
L
ROW/COL Data Out
Write: (Early Write)
L
L
L
X
ROW/COL Data-In
Read Write
L
L
H
L
L
H
ROW/COL Data-Out, Data-In
EDO-Page-
Mode Read
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
H
L
L
ROW/COL
COL
Data-Out
Data-Out
EDO-Page-
Mode Write
1st Cycle
2nd Cycle
L
L
H
L
H
L
L
L
X
X
ROW/COL
COL
Data-In
Data-In
EDO-Page-
Mode Read-
Write
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
L
H
L
L
H
L
H
ROW/COL
COL
Data-Out, Data-In
Data-Out, Data-In
Hidden
Refresh
Read
Write
L
H
L
L
H
L
L
L
H
L
L
X
ROW/COL
ROW/COL
Data-Out
Data-In
1
RAS-Only Refresh
L
H
X
X
ROW
High-Z
CBR Refresh
H
L
L
X
X
High-Z
Notes:
1. EARLY WRITE only.
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 5 -
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, V
CC
=3.3V
0.3V, V
SS
=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max.
Unit Notes
I
LI
Input Leakage Current
(any input pin)
V
SS
V
IN
V
CC
-5
+5
A
I
LO
Output Leakage Current
(for High-Z State)
V
SS
V
out
V
CC
RAS , CAS at V
IH
-5
+5
A
I
CC1
V
CC
Supply Current,
Operating
t
RC
= t
RC
(min.)
t
RAC
= 60ns
t
RAC
= 70ns
140
130
mA
1,2
I
CC2
V
CC
Supply Current,
TTL Standby
RAS , CAS at V
IH
other inputs
V
SS
2
mA
I
CC3
V
CC
Supply Current,
RAS -Only Refresh
t
RC
= t
RC
(min.)
t
RAC
= 60ns
t
RAC
= 70ns
140
130
mA
2
I
CC4
V
CC
Supply Current,
Fast Page Mode Operation
Minimum Cycle
t
RAC
= 60ns
t
RAC
= 70ns
140
130
mA
1,2
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
Other inputs
V
SS
RAS =V
IH
, CAS =V
IL
2
mA
1
I
CC6
V
CC
Supply Current,
CMOS Standby
RAS
V
CC
-0.2V,
CAS
V
CC
-0.2V,
All other inputs
V
SS
1
mA
V
IL
Input Low Voltage
-0.3
+0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
4
V
OL
Output Low Voltage
I
OL
= 2.0mA
0.4
V
V
OH
Output High Voltage
I
OH
= -2.0mA
2.4
V
Notes:
1.I
CC
is dependent on output loading when the device output is selected. Specified I
CC(max.)
is measured with the
output open.
2.I
CC
is dependent upon the number of address transitions specified I
CC(max.)
is measured with a maximum of one
transition per address cycle in random Read/Write and Fast Page Mode.
3.Specified V
IL(min.)
is steady state operation. During transitions V
IL(min.)
may undershoot to 0.3V for a period not
to exceed 20ns. All AC parameters are measured with V
IL(min.)
V
SS
and V
IH(max.)
V
CC
.
4.Specified V
IH
(max.) is steady state operation . During transitions V
IH
(max.) may overshoot to V
CC
+0.9V for a
period not to exceed 10ns. All AC parameters are measured with V
IL
(min.)
V
SS
and VIH(max.)
V
CC
.
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 6 -
AC Characteristics (0

C

T
A

70

C,See note 1,2)
Test condition:V
CC
=3.3V
0.3V V
IH
/V
IL
= 3.0/0V , V
OH
/V
OL
= 2.0/0.8V
60
70
Parameter
Symbol
Min.
Max.
Min.
Max.
Unit
Notes
Read or Write Cycle Time
t
RC
110
130
ns
Read Modify Write Cycle Time
t
RWC
155
185
ns
RAS Precharge Time
t
RP
40
50
ns
RAS Pulse Width
t
RAS
60
10k
70
10k
ns
Access Time from RAS
t
RAC
60
70
ns
3, 4, 9
Access Time from CAS
t
CAC
15
20
ns
3, 4
Access Time from Column Address
t
AA
30
35
ns
3, 9
CAS to Output Low-Z
t
CLZ
0
0
ns
3
RAS Hold Time
t
RSH
15
20
ns
CAS Hold Time
t
CSH
60
70
ns
CAS Pulse Width
t
CAS
15
10k
20
10k
ns
RAS to CAS Delay Time
t
RCD
20
45
20
50
ns
RAS to Column Address Delay Time
t
RAD
15
30
15
35
ns
7
CAS to RAS Precharge Time
t
CRP
5
5
ns
Row Address Set-Up Time
t
ASR
0
0
ns
Row Address Hold Time
t
RAH
10
10
ns
Column Address Set-Up Time
t
ASC
0
0
ns
Column Address Hold Time
t
CAH
10
15
ns
Column Address to RAS Lead Time
t
RAL
30
35
ns
Read Command Set-Up Time
t
RCS
0
0
ns
Read Command Hold Time Referenced to CAS
t
RCH
0
0
ns
4
Read Command Hold Time Referenced to RAS
t
RRH
0
0
ns
4
Write Command Set-Up Time
t
WCS
0
0
ns
8, 9
Write Command Hold Time
t
WCH
10
15
ns
Write Command Pulse Width
t
WP
10
15
ns
Write Command to RAS Lead Time
t
RWL
15
20
ns
Write Command to CAS Lead Time
t
CWL
15
20
ns
Data Set-Up Time
t
DS
0
0
ns
Data Hold Time
t
DH
10
15
ns
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 7 -
AC Characteristics
60
70
Parameter
Symbol
Min.
Max.
Min.
Max.
Unit
Notes
RAS to WE Delay Time
t
RWD
85
100
ns
CAS to WE Delay Time
t
CWD
40
50
ns
Column Address to WE Delay Time
t
AWD
55
65
ns
CAS Precharge to WE Delay
t
CPWD
60
70
ns
RAS to CAS Precharge Time
t
RPC
5
5
ns
CAS Precharge Time ( CAS Before RAS
Counter Test Cycle)
t
CPT
20
30
ns
Access Time from CAS Precharge
t
CPA
35
40
ns
Page Mode Cycle Time
t
PC
40
45
ns
Page Mode Read-Modify-Write Cycle Time
t
PRWC
85
100
ns
CAS Precharge Time (Page Mode)
t
CP
10
10
ns
RAS Pulse Width (Page Mode Only)
t
RASP
60
100k
70
100k
ns
RAS Hold Time from CAS Precharge
t
RHCP
35
40
ns
Access Time from OE
t
OEA
15
20
ns
8
OE to Data Delay Time
t
OED
15
20
ns
OE to Output High-Z
t
OEZ
0
15
0
20
ns
OE Command Hold Time
t
OEH
15
20
ns
CAS Set-Up Time for CAS -Before- RAS Cycle
t
CSR
5
5
ns
CAS Hold Time for CAS -Before- RAS Cycle
t
CHR
10
15
ns
WE to RAS Precharge Time ( CAS Before
RAS Refresh )
t
WRP
10
10
ns
WE to RAS Hold Time ( CAS Before RAS
Refresh )
t
WRH
10
10
ns
Transition Time
t
T
3
50
3
50
ns
Refresh Period (2,048 cycles)
t
REF
16
16
ms
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 8 -
Notes
1. An initial pause of 100
s is required after power-up followed by any 8 RAS only Refresh or CAS
before RAS Refresh cycles to initialize the internal circuit.
2. V
IH(min.)
and V
IL(min.)
are reference levels for measuring timing of input signals. Transition times
are measured between V
IH(min.)
and V
IL(max.)
, AC measurements assume t
T
= 5ns.
3. Measured with an equivalent to 1 TTL loads and 50pF.
4. For read cycles, the access time is defined as follows:
Input Conditions
Access Time
t
RAD
t
RAD(MAX.)
and t
RCD
t
RCD(MAX.)
t
RAC(MAX.)
t
RAD(max.)
< t
RAD
and t
RCD
t
RCD(MAX.)
t
AA(MAX.)
t
RCD(max.)
< t
RCD
t
CACMAX.)
t
RAD(MAX.)
and t
RCD(MAX.)
indicate the points which the access time changes and are not the limits of
operation.
5. t
WCS
,t
RWD
,t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data sheet
as electric characteristics only. If t
WCS
t
WCS(min.)
, the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle. If t
CWD
t
CWD(min.)
,t
RWD
t
RWD
(min.)
and
t
AWD
t
AWD(min.)
, then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6. t
AR
,t
WCR
, and t
DHR
are referenced to t
RAD(max.)
.
7. t
OFF(max.)
and t
OEZ(max.)
define the time at which the output achieves the open circuit condition and are
not referenced to V
OH
or V
OL
.
8. t
CRP(min)
requirement should be applicable for RAS , CAS cycle preceded by any cycles.
9. Either t
RCH(min.)
or t
RRH(min.)
must be satisfied for a read cycle.
10. t
WP(min.)
is applicable for late write cycle or read modify write cycle. In early write cycles,t
WCH(min.)
should be satisfied.
11.This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in
late write or read modify write cycles.
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 9 -
Read Cycle
ROW
ADDRESS
COLUMN
ADDRESS
DATA-OUT
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
RSH
t
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCH
t
RRH
t
AR
t
RCS
t
AA
t
OEA
t
OFF
t
OEZ
t
CAC
t
CLZ
t
RAC
Don't Care
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
OPEN
Early Write Cycle NOTE :
D
OUT
= Open
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 10 -
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
CWL
t
RWL
t
WCR
t
WCH
t
WP
t
WCS
t
AR
t
DS
t
DH
t
DHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
Late Write Cycle ( OE Controlled Write)
NOTE : D
OUT
= Open
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 11 -
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
COLUMN
ADDRESS
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 12 -
Fast Page Read Cycle
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Don't Care
t
RCS
t
RCH
t
RCS
t
RCS
t
RCH
t
RRH
t
OEA
t
CAC
t
OEA
t
CAC
t
CLZ
t
RAC
t
AA
t
OEZ
t
OFF
t
AA
t
CLZ
t
OEZ
t
OEZ
t
OFF
t
OFF
t
CLZ
t
AA
VALID
DATA-UOT
VALID
DATA-UOT
VALID
DATA-UOT
Fast Page Write Cycle
NOTE : D
OUT
= Open
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
t
WCS
t
WP
t
WCH
t
WCS
t
WCS
t
WCH
t
WCH
t
WP
t
WP
t
DS
t
DS
t
DS
t
DH
t
DS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
t
CWL
t
CWL
t
CWL
t
RWL
t
RHCP
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 13 -
Fast Page Mode Late Write Cycle
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
RSH
t
ASC
t
ASC
t
CAH
t
CAH
t
DS
t
DS
t
DH
t
DS
t
DH
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
Don't Care
t
CSH
t
RHCP
t
CRP
VALID
DATA-IN
VALID
DATA-IN
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCS
t
WP
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RCS
t
RCS
t
RWL
t
OEH
t
OEH
t
OEH
t
OED
t
OED
t
DH
t
OED
Hi-Z
Hi-Z
Hi-Z
Fast Page Read - Modify - Write Cycle
t
RASP
t
RP
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
Don't Care
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
PRWC
t
RCS
t
WP
t
CWL
t
WP
t
CWL
t
RWL
t
CWD
t
AWD
t
RWD
t
OEA
t
CWD
t
AWD
t
CPWD
t
OEA
t
OEH
t
RAC
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
CLZ
t
CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR.
COL.
ADDR.
COL.
ADDR.
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 14 -
CAS Before RAS Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
CSR
t
CSR
t
CHR
t
CHR
t
RPC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
RAS -Only Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
CRP
t
ASR
t
ASR
t
RAH
t
RAH
ROW
ROW
Address
V
IH-
V
IL-
Hidden Refresh Cycle ( Read )
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RAC
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
CAC
t
RCS
t
ASC
t
CAH
t
ASR
t
CAH
t
RAD
t
RAL
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
t
RC
t
WHR
t
AA
t
OEA
t
CLZ
t
OFF
t
OEZ
DATA-OUT
OPEN
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 15 -
Hidden Refresh Cycle ( Write )
NOTE : D
OUT
=Open
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
DH
t
WP
t
WCH
t
WCS
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
DATA-IN
t
RC
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 16 -
CAS - Before RAS Refresh Counter Test Cycle
t
CAS
t
CPT
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RP
t
RAS
t
CSR
t
CHR
t
RSH
t
RAL
t
ASC
t
AA
t
CAC
t
RCS
t
RRH
t
RCH
t
WRP
t
WRH
t
WRH
t
WRP
t
OEA
t
CEZ
t
OEZ
t
CLZ
t
RWL
t
CWL
t
WCH
t
WCS
t
WP
t
DS
t
DH
t
RCS
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
DH
t
DS
t
OED
t
OEZ
t
CLZ
t
CAC
t
AA
t
OEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
t
CAH
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 17 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
PACKAGE
GLT441L08-60J4
60ns
Normal
FPM
28L 400mil SOJ
GLT441L08-70J4
70ns
Normal
FPM
28L 400mil SOJ
GLT441L08-60TC
60ns
Normal
FPM
28L 400mil TSOP II
GLT441L08-70TC
70ns
Normal
FPM
28L 400mil TSOP II
Parts Numbers (Top Mark) Definition :
GLT 4 41 L 08 - 60 J4
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
G -LINK
GLT441L08
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2001 (Rev. 1.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 18 -
Package Information
400mil 28 Lead Small Outline J-form Package (SOJ)
400mil 28 Lead Thin Small Outline Package (TSOP) Type II
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