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Datasheet: GLT44108-40J4 (G-Link Technology Corp.)

40ns; 512K X 8 CMOS Dynamic RAM With Fast Page Mode

 

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G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
524
,288 words by 8 bits organization.
Fast access time and cycle time.
Low power dissipation.
Operating Current-150mA max.
TTL Standby Current-2mA max.
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
1024 refresh cycles/16ms.
Available in 28pin 400 mil SOJ
Single +5.0V
10% Power Supply.
All inputs and Outputs are TTL-
compatible.
Fast Page Mode supports sustained data
rates up to 50MHZ.
The GLT44108 is a 524,288 x 8 bit high-
performance CMOS dynamic random access
memory. The GLT44108 offers Fast Page mode with
asymmetric address and accepts 512-cycle refresh in
8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 8 bits
within a page, with cycle times as short as 22ns.
The GLT44108 is best suited for graphics, digital
signal processing and high performance peripherals.
PIN CONFIGURATION :
V
cc
DQ
0
A9
A
0
A
1
A
2
A
3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
26
25
24
23
NC
A
8
A
7
V
SS
DQ
7
DQ
1
NC
V
CC
DQ
6
A
6
A
5
V
SS
14
27
28
DQ
5
DQ
4
CAS
OE
20
A
4
7
DQ
3
DQ
2
WE
RAS
GLT44108
28 Lead SOJ
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
HIGH PERFORMANCE
-40
-50
-60
Max. RAS
Access Time, (t
RAC
)
40 ns
50 ns
60 ns
Max. Column Address Access Time, (t
AA
)
20 ns
25 ns
30 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
22 ns
31 ns
40 ns
Min. Read/Write Cycle Time, (t
RC
)
75 ns
90 ns
110 ns
Max. CAS Access Time (t
CAC
)
12 ns
13 ns
15 ns
Pin Descriptions:
Name
Function
A
0
A
9
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
DQ
0
- DQ
7
Data Inputs / Outputs
V
CC
+5V Power Supply
V
SS
Ground
Block Diagram:
1 0 2 4
O E
C L O C K
G E N E R A T O R
W E
C L O C K
G E N E R A T O R
C A S
C L O C K
G E N E R A T O R
R A S
C L O C K
G E N E R A T O R
D a t a I / O B U S
C O L U M N D E C O D E R S
S E N S E A M P L I F I E R S
I / O
B U F F E R
M E M O R Y
A R R A Y
R E F R E S H
C O U N T E R
.
.
X
0
- x
9
5 1 2 8
Y
0
- Y
8
9
I / O 0
I / O 1
I / O 2
I / O 3
I / O 4
I / O 5
I / O 6
I / O 7
O E
W E
R A S
C A S
V
C C
V
S S
A
0
A
1
A
8
A
9
A D D R E S S B U F F E R S
A N D P R E D E C O D E R S
R O W
D E C O D E R S
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings*
Capacitance*
T
A
=25
C, V
CC
=5V
10%, V
SS
=0V
Operating Temperature, T
A
(ambient)
......................................-10
C to +80
C
Storage Temperature(plastic)....-55
C to +150
C
Voltage Relative to V
SS
...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS
,
CAS
,
WE
,
OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note:Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Electrical Specifications
*Note: Capacitance is sampled and not 100% tested
l
All voltages are referenced to GND.
l
After power up, wait more than 200
s and then, execute eight CAS before
RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
DC and Operating Characteristics (1-2)
TA = 0
C to 70
C, V
CC
=5V
10%, V
SS
=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max. Unit Notes
I
LI
Input Leakage Current
(any input pin)
0V
V
IN
5.5V
(All other pins not under
test=0V)
-10
+10
A
I
LO
Output Leakage Current
(for High-Z State)
0V
V
out
5.5V
Output is disabled (Hiz)
-10
+10
A
I
CC1
Operating Current,
Random READ/WRITE
t
RC
= t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
150
140
120
mA
1,2
I
CC2
Standby Current,(TTL)
RAS , CAS , at V
IH
other inputs
V
SS
2
mA
I
CC3
Refresh Current,
RAS -Only
RAS
cycling,
CAS at V
IH
t
RC
= t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
150
140
120
mA
2
I
CC4
Operating Current,
FAST Page Mode
RAS
at V
IL
,
CAS ,address
cycling:t
PC
=t
PC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
150
140
120
mA
1,2
I
CC5
Refresh Current,
CAS Before RAS
RAS ,
CAS ,
address cycling:
t
RC
=t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
150
140
120
mA
1
I
CC6
Standby Current, (CMOS)
RAS
V
CC
-0.2V,
CAS
V
CC
-0.2V,
All other inputs
V
SS
1
mA
V
IL
Input Low Voltage
-1
+0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+1
V
3
V
OL
Output Low Voltage
I
OL
= 4.2mA
0.4
V
V
OH
Output High Voltage
I
OH
= -5mA
2.4
V
Notes:
1.I
CC
is dependent on output loading when the device output is selected. Specified I
CC(max.)
is measured with the output
open.
2.I
CC
is dependent upon the number of address transitions specified. I
CC(max.)
is measured with a maximum of one transition
per address cycle in random Read/Write and Fast Page Mode.
3. Specified V
IL(min.)
is steady state operation. During transitions, V
IL(min.)
may undershoot to -1.0V for a period
not to exceed 20ns.All AC parameters are measured with V
IL(min.)
V
ss
and V
IH(max.)
V
cc
.
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
AC Characteristics (0

C

T
A

70

C,See note 1,2)
Test condition:V
CC
=5.0V
10%, V
IH
/V
IL
=2.4V/0.8V,V
OH
/V
OL
=2.0V/0.8V
Parameter
40 ns
50 ns
60 ns
Symbol
MIN.
MAX.
MIN.
MAX.
MIN.
MAX. Unit
Notes
Read/Write Cycle Time
t
RC
75
-
90
-
110
-
ns
Read Midify Write Cycle Time
t
RWC
120
-
140
-
160
-
ns
Access Time from RAS
t
RAC
-
40
-
50
-
60
ns
3,4
Access Time from CAS
t
CAC
-
12
-
13
-
15
ns
3,4
Access Time from Column Address
t
AA
-
20
-
25
-
30
ns
3,4
CAS to Output in Low-Z
t
CLZ
0
-
0
-
0
-
ns
3
Output Buffer Turn-off Delay from CAS
t
OFF
0
8
0
10
0
13
ns
7
Transition Time(Rise and Fall)
t
T
3
50
3
50
3
50
ns
2
RAS Precharge Time
t
RP
25
-
30
-
40
-
ns
RAS Pulse Width
t
RAS
40
10000
50
10000
60
10000
ns
RAS Hold Time
t
RSH
12
-
13
-
15
-
ns
CAS Hold Time
t
CSH
40
-
50
-
60
-
ns
CAS Pulse Width
t
CAS
12
10000
13
10000
15
10000
ns
RAS to CAS Delay Time
t
RCD
16
30
18
37
20
45
ns
4
RAS to Column Address Delay Time
t
RAD
11
22
13
25
15
30
ns
4
CAS to RAS Precharge Time
t
CRP
5
-
5
-
5
-
ns
8
Row Address Setup Time
t
ASR
0
-
0
-
0
-
ns
Row Address Hold Time
t
RAH
6
-
8
-
10
-
ns
Column Address Setup Time
t
ASC
0
-
0
-
0
-
ns
Column Address Hold Time
t
CAH
6
-
8
-
10
-
ns
Column Address Hold Time Referenced
to RAS
t
AR
30
-
40
-
45
-
ns
Column Address Lead Time Referenced
to RAS
t
RAL
20
-
25
-
30
-
ns
Read Command Setup Time
t
RCS
0
-
0
-
0
-
ns
Read Command Hold Time Referenced
to RAS
t
RRH
0
-
0
-
0
-
ns
9
Read Command Hold Time Referenced
to CAS
t
RCH
0
-
0
-
0
-
ns
9
WE Hold Time Referenced to CAS
t
WCH
6
-
7
-
10
-
ns
10
Write Command Hold Time Referenced
to RAS
t
WCR
30
-
40
-
45
-
ns
5
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
Parameter
40 ns
50 ns
60 ns
Symbol
MIN.
MAX.
MIN.
MAX.
MIN.
MAX. Unit
Notes
WE Pulse Width
t
WP
6
-
7
-
10
-
ns
10
WE Lead Time Referenced to RAS
t
RWL
13
-
17
-
15
-
ns
WE Lead Time Referenced to CAS
t
CWL
13
-
14
-
15
-
ns
Data-In Setup Time
t
DS
0
-
0
-
0
-
ns
11
Data-In Hold Time
t
DH
6
-
7
-
10
-
ns
11
Data Hold Time Referenced to RAS
t
DHR
33
-
40
-
45
-
ns
6
Refresh Time(256cycles)
t
REF
-
8
-
8
-
8
ms
WE Setup Time
t
WCS
0
-
0
-
0
-
ns
5
RAS to WE Delay Time
t
RWD
60
-
70
-
85
-
ns
5
CAS to WE Delay Time
t
CWD
28
-
33
-
38
-
ns
5
Column Address to WE Delay Time
t
AWD
38
-
43
-
53
-
ns
5
CAS Setup Time( CAS before RAS
Refresh)
t
CSR
5
-
5
-
5
-
ns
CAS Hold Time( CAS before RAS
Refresh)
t
CHR
10
-
10
-
10
-
ns
RAS to CAS Precharge Time
t
RPC
5
-
5
-
5
-
ns
CAS Precharge Time(CBR Counter Test
Cycle)
t
CPT
20
-
20
-
20
-
ns
Access Time from CAS Precharge
t
CPA
-
25
-
30
-
35
ns
3
Fast Page mode Read/Write Cycle Time
t
PC
30
-
35
-
40
-
ns
Fast Page mode Read Modify Write Cycle
Time
t
PRWC
65
-
80
-
90
-
ns
CAS Precharge Time(Fast Page mode)
t
CP
7
-
8
-
10
-
ns
RAS Pulse Width(Fast Page mode)
t
RASP
40
125000
50
125000
60
125000
ns
RAS Hold Time from CAS Precharge
t
RHCP
25
-
30
-
35
-
ns
Access Time from OE
t
OEA
-
10
-
13
-
15
ns
OE to Delay Time
t
OED
8
-
10
-
13
-
ns
Output Buffer Turn-off Delay Time from
OE
t
OEZ
0
8
0
10
0
13
ns
7
OE Hold Time
t
OEH
0
-
0
-
0
-
ns
WE Hold Time(Hidden Refresh Cycle)
t
WHR
15
-
15
-
15
-
ns
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
Notes
1. An initial pause of 200
s is required after power-up followed by any 8 RAS
only Refresh or CAS
before RAS Refresh cycles to initialize the internal circuit.
2. V
IH(min.)
and V
IL(min.)
are reference levels for measuring timing of input signals. Transition times
are measured between V
IH(min.)
and V
IL(max.)
are assumed to be 5ns for all inputs.
3. Measured with an equivalent to 1 TTL loads and 50pF.
4. For read cycles, the access time is defined as follows:
Input Conditions
Access Time
t
RAD
t
RAD(MAX.)
and t
RCD
t
RCD(MAX.)
t
RAC(MAX.)
t
RAD(max.)
< t
RAD
and t
RCD
t
RCD(MAX.)
t
AA(MAX.)
t
RCD(max.)
< t
RCD
t
CACMAX.)
t
RAD(MAX.)
and t
RCD(MAX.)
indicate the points which the access time changes and are not the limits of
operation.
5. t
WCS
,t
RWD
,t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data sheet
as electric characteristics only. If t
WCS
t
WCS(min.)
, the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle.If t
CWD
t
CWD
(
min.)
,t
RWD
t
RWD
(min.)
and
t
AWD
t
AWD(min.)
, then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6. t
AR
,t
WCR
, and t
DHR
are referenced to t
RAD(max.)
.
7. t
OFF(max.)
and t
OEZ(max.)
define the time at which the output achieves the open circuit condition and are
not referenced to V
OH
or V
OL
.
8. t
CRP(min)
requirement should be applicable for RAS ,
CAS cycle preceded by any cycles.
9. Either t
RCH(min.)
or t
RRH(min.)
must be satisfied for a read cycle.
10. t
WP(min.)
is applicable for late write cycle or read modify write cycle. In early write cycles,t
WCH(min.)
should be satisfied.
11.This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in
late write or read modify write cycles.
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
Read Cycle
ROW
ADDRESS
COLUMN
ADDRESS
DATA-OUT
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
RSH
t
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCH
t
RRH
t
AR
t
RCS
t
AA
t
OEA
t
OFF
t
OEZ
t
CAC
t
CLZ
t
RAC
Don't Care
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
OPEN
Early Write Cycle NOTE :
D
OUT
= Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
CWL
t
RWL
t
WCR
t
WCH
t
WP
t
WCS
t
AR
t
DS
t
DH
t
DHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
Late Write Cycle ( OE Controlled Write)
NOTE : D
OUT
= Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
COLUMN
ADDRESS
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Fast Page Read Cycle
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Don't Care
t
RCS
t
RCH
t
RCS
t
RCS
t
RCH
t
RRH
t
OEA
t
CAC
t
OEA
t
CAC
t
CLZ
t
RAC
t
AA
t
OEZ
t
OFF
t
AA
t
CLZ
t
OEZ
t
OEZ
t
OFF
t
OFF
t
CLZ
t
AA
VALID
DATA-UOT
VALID
DATA-UOT
VALID
DATA-UOT
Fast Page Write Cycle
NOTE : D
OUT
= Open
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
t
WCS
t
WP
t
WCH
t
WCS
t
WCS
t
WCH
t
WCH
t
WP
t
WP
t
DS
t
DS
t
DS
t
DH
t
DS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
t
CWL
t
CWL
t
CWL
t
RWL
t
RHCP
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Fast Page Mode Late Write Cycle
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
RSH
t
ASC
t
ASC
t
CAH
t
CAH
t
DS
t
DS
t
DH
t
DS
t
DH
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
Don't Care
t
CSH
t
RHCP
t
CRP
VALID
DATA-IN
VALID
DATA-IN
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCS
t
WP
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RCS
t
RCS
t
RWL
t
OEH
t
OEH
t
OEH
t
OED
t
OED
t
DH
t
OED
Hi-Z
Hi-Z
Hi-Z
Fast Page Read - Modify - Write Cycle
t
RASP
t
RP
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
Don't Care
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
PRWC
t
RCS
t
WP
t
CWL
t
WP
t
CWL
t
RWL
t
CWD
t
AWD
t
RWD
t
OEA
t
CWD
t
AWD
t
CPWD
t
OEA
t
OEH
t
RAC
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
CLZ
t
CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR.
COL.
ADDR.
COL.
ADDR.
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
CAS Before RAS Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
CSR
t
CSR
t
CHR
t
CHR
t
RPC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
RAS -Only Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
CRP
t
ASR
t
ASR
t
RAH
t
RAH
ROW
ROW
Address
V
IH-
V
IL-
Hidden Refresh Cycle ( Read )
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RAC
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
CAC
t
RCS
t
ASC
t
CAH
t
ASR
t
CAH
t
RAD
t
RAL
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
t
RC
t
WHR
t
AA
t
OEA
t
CLZ
t
OFF
t
OEZ
DATA-OUT
OPEN
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
Hidden Refresh Cycle ( Write )
NOTE : D
OUT
=Open
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
DH
t
WP
t
WCH
t
WCS
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
DATA-IN
t
RC
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
CAS - Before RAS Refresh Counter Test Cycle
t
CAS
t
CPT
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RP
t
RAS
t
CSR
t
CHR
t
RSH
t
RAL
t
ASC
t
AA
t
CAC
t
RCS
t
RRH
t
RCH
t
WRP
t
WRH
t
WRH
t
WRP
t
OEA
t
CEZ
t
OEZ
t
CLZ
t
RWL
t
CWL
t
WCH
t
WCS
t
WP
t
DS
t
DH
t
RCS
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
DH
t
DS
t
OED
t
OEZ
t
CLZ
t
CAC
t
AA
t
OEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
t
CAH
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
PACKAGE
GLT44108-40J4
40ns
Normal
FPM
SOJ 400mil 28L
GLT44108-50J4
50ns
Normal
FPM
SOJ 400mil 28L
GLT44108-60J4
60ns
Normal
FPM
SOJ 400mil 28L
Parts Numbers (Top Mark) Definition :
GLT 4 41 08 - 40 J4
Note : C
CDROM , H
HDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
G -LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
Package Information
400mil 28 Lead Small Outline J-form Package (SOJ)
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