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Datasheet: GLT440L08-60J4 (G-Link Technology Corp.)

 

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G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
524
,288 words by 8 bits organization.
Fast access time and cycle time.
Low power dissipation.
Operating Current-160mA max.
TTL Standby Current-2mA max.
Read-Modify-Write,
RAS
- Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
1024
refresh cycles/16ms.
Available in 28-pin 400milSOJ
Single +3V
3.3V Power Supply.
All inputs and Outputs are TTL-
compatible.
Extended Data-Out(EDO) Page Mode
Operation.
The GLT440L08 is a 524,288 x 8 bit high-
performance CMOS dynamic random access
memory. The GLT440L08 offers Fast Page mode
with Extended Data Output has asymmetric address
and accepts 1024-cycle refresh in 16ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 8 bits
within a page, with cycle times as short as 25ns.
PIN CONFIGURATION :
V
cc
DQ
0
A9
A
0
A
1
A
2
A
3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
26
25
24
23
NC
A
8
A
7
V
SS
DQ
7
DQ
1
NC
V
CC
DQ
6
A
6
A
5
V
SS
14
27
28
DQ
5
DQ
4
CAS
OE
20
A
4
7
DQ
3
DQ
2
WE
RAS
GLT440L08
28 Lead SOJ
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
HIGH PERFORMANCE
-60
-70
-80
Max.
RAS
Access Time, (t
RAC
)
60 ns
70 ns
80 ns
Max. Column Address Access Time, (t
AA
)
30 ns
35 ns
40 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
25 ns
30 ns
35 ns
Min. Read/Write Cycle Time, (t
RC
)
104 ns
124 ns
144 ns
Max.
CAS
Access Time (t
CAC
)
15 ns
20 ns
20 ns
Pin Descriptions:
Name
Function
A
0
A
9
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
DQ
0
- DQ
7
Data Inputs / Outputs
V
CC
3.3V Power Supply
V
SS
Ground
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings*
Capacitance*
T
A
=25
C, V
CC
=3.3V
.0.3V, V
SS
=0V
Operating Temperature, T
A
(ambient)
...................................
...
.0
C to +70
C
Storage Temperature(plastic). -55
C to +150
C
Voltage Relative to V
SS
......... ......-1.0V to + 4.6V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS
,
CAS
,
WE
,
OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note: Operation above Absolute Maximum Ratings
can adversely affect device reliability.
Electrical Specifications
*Note: Capacitance is sampled and not 100% tested
l
All voltages are referenced to GND.
l
After power up, wait more than 200
s and then, execute eight
CAS
before
RAS
or
RAS
only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram:
1 0 2 4
O E
C L O C K
G E N E R A T O R
W E
C L O C K
G E N E R A T O R
C A S
C L O C K
G E N E R A T O R
R A S
C L O C K
G E N E R A T O R
D a t a I / O B U S
C O L U M N D E C O D E R S
S E N S E A M P L I F I E R S
I / O
B U F F E R
M E M O R Y
A R R A Y
R E F R E S H
C O U N T E R
.
.
X
0
- x
9
5 1 2 8
Y
0
- Y
8
9
I / O 0
I / O 1
I / O 2
I / O 3
I / O 4
I / O 5
I / O 6
I / O 7
O E
W E
R A S
C A S
V
C C
V
S S
A
0
A
1
A
8
A
9
A D D R E S S B U F F E R S
A N D P R E D E C O D E R S
R O W
D E C O D E R S
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
Truth Table: GLT440L08
Function
RAS
CAS
WE
OE
ADDRESS
DQs
Notes
Standby
H
H
X
X
X
High-Z
Read
L
L
H
L
ROW/COL Data Out
Write: (Early Write)
L
L
L
X
ROW/COL Data-In
Read Write
L
L
H
L
L
H
ROW/COL Data-Out, Data-In
EDO-Page-
Mode Read
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
H
L
L
ROW/COL
COL
Data-Out
Data-Out
EDO-Page-
Mode Write
1st Cycle
2nd Cycle
L
L
H
L
H
L
L
L
X
X
ROW/COL
COL
Data-In
Data-In
EDO-Page-
Mode Read-
Write
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
L
H
L
L
H
L
H
ROW/COL
COL
Data-Out, Data-In
Data-Out, Data-In
Hidden
Refresh
Read
Write
L
H
L
L
H
L
L
L
H
L
L
X
ROW/COL
ROW/COL
Data-Out
Data-In
1
RAS-Only Refresh
L
H
X
X
ROW
High-Z
CBR Refresh
H
L
L
X
X
High-Z
Notes:
1. EARLY WRITE only.
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, V
CC
=3.3V
0.3V, V
SS
=0 V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max. Unit Notes
I
LI
Input Leakage Current
(any input pin)
0V
V
IN
5.5V
(All other pins not under
test=0V)
-5
+5
A
I
LO
Output Leakage Current
(for High-Z State)
0V
V
out
5.5V
Output is disabled (Hiz)
-5
+5
A
I
CC1
Operating Current,
Random READ/WRITE
t
RC
= t
RC
(min.)
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 80ns
140
130
120
mA
1,2
I
CC2
Standby Current,(TTL)
RAS
,
CAS
, at V
IH
other inputs
V
SS
2
mA
I
CC3
Refresh Current,
RAS
-Only
RAS
cycling,
CAS
at V
IH
t
RC
= t
RC
(min.)
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 80ns
140
130
120
mA
2
I
CC4
Operating Current,
EDO Page Mode
RAS
at V
IL
,
CAS
,address cycling:
t
PC
= t
PC
(min.)
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 80ns
140
130
120
mA
1,2
I
CC5
Refresh Current,
CAS
Before
RAS
RAS
,
CAS
,
address cycling:
t
RC
= t
RC
(min.)
t
RAC
= 60ns
t
RAC
= 70ns
t
RAC
= 80ns
140
130
120
mA
1
I
CC6
Standby Current, (CMOS)
RAS
V
CC
-0.2V,
CAS
V
CC
-0.2V,
All other inputs
V
SS
1
mA
1,5
V
CC
Supply Voltage
3V
3.3V
3.6V
V
V
IL
Input Low Voltage
-0.3
+0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
3
V
OL
Output Low Voltage
I
OL
= 2 mA
0.4
V
V
OH
Output High Voltage
I
OH
= -2 mA
2
V
Notes:
1.

I
CC
is dependent on output loading when the device output is selected. Specified I
CC(max.)
is measured with the output
open.
2.

I
CC
is dependent upon the number of address transitions specified. I
CC(max.)
is measured with a maximum of one
transition per address cycle in random Read/Write and EDO Page Mode.
3. Specified V
IL(min.)
is steady state operation. During transitions,
VIL(min.)
may undershoot to -1.0V for a period
not to exceed 20ns All AC parameters are measured with V
IL(min.)
V
ss
and V
IH(max.)
V
cc
.
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
AC Characteristics
T
A
= 0
C to 70
C , V
CC
= 3.3V
0.3V, V
IH
/V
IL
= 3.0/0 V, V
OH
/V
OL
= 2.0/0.8V
An initial pause of 200
s and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
60
70
80
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit Notes
Read or Write Cycle Time
t
RC
104
124
144
ns
Read Modify Write Cycle Time
t
RWC
140
170
190
ns
RAS
Precharge Time
t
RP
40
50
60
ns
RAS
Pulse Width
t
RAS
60
10k
70
10k
80
10k
ns
Access Time from
RAS
t
RAC
60
70
80
ns
1,2,3
Access Time from
CAS
t
CAC
15
20
20
ns 1,5,10
Access Time from Column Address
t
AA
30
35
40
ns
1,5,6
CAS
to Output Low-Z
t
CLZ
3
3
3
ns
CAS
to Output High-Z
t
CEZ
3
15
3
20
3
20
ns
RAS
Hold Time
t
RSH
15
20
20
ns
RAS
Hold Time Referenced to
OE
t
ROH
10
10
ns
CAS
Hold Time
t
CSH
45
50
70
ns
CAS
Pulse Width
t
CAS
10
10k
15
10k
20
80k
ns
RAS
to CAS Delay Time
t
RCD
20
45
20
50
20
60
ns
RAS
to Column Address Delay Time
t
RAD
15
30
15
35
15
40
ns
7
CAS
to RAS Precharge Time
t
CRP
5
5
5
ns
Row Address Set-Up Time
t
ASR
0
0
0
ns
Row Address Hold Time
t
RAH
10
10
10
ns
Column Address Set-Up Time
t
ASC
0
0
0
ns
Column Address Hold Time
t
CAH
10
15
15
ns
Column Address to RAS Lead Time
t
RAL
30
35
40
ns
Column Address Hold Time Referenced to
RAS
t
AR
45
50
60
ns
Read Command Set-Up Time
t
RCS
0
0
0
ns
Read Command Hold Time Referenced to
CAS
t
RCH
0
0
0
ns
4
Read Command Hold Time Referenced to
RAS
t
RRH
0
0
0
ns
4
Write Command Set-Up Time
t
WCS
0
0
0
ns
8,9
Write Command Hold Time
t
WCH
10
15
15
ns
Write Command Pulse Width
t
WP
10
15
15
ns
Write Command to
RAS
Lead Time
t
RWL
15
30
20
ns
Write Command to
CAS
Lead Time
t
CWL
13
15
20
ns
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
AC Characteristics
60
70
80
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit Notes
Data Set-Up Time
t
DS
0
0
0
ns
Data Hold Time
t
DH
10
15
15
ns
Data Hold Time Referenced to
RAS
t
DHR
45
50
60
ns
RAS
to
WE
E Delay Time
t
RWD
79
94
99
ns
CAS
to
WE
Delay Time
t
CWD
34
44
44
ns
Column Address to
WE
Delay Time
t
AWD
49
59
64
ns
RAS
to
CAS
Precharge Time
t
RPC
0
0
5
ns
Access Time from
CAS
Precharge
t
CPA
35
40
45
ns
EDO Page Mode Cycle Time
t
PC
25
30
35
ns
EDO Page Mode Read-Modify-Write Cycle Time
t
PRWC
56
71
81
ns
CAS
Precharge Time (EDO Page Mode)
t
CP
10
10
10
ns
RAS
Pulse Width (EDO Page Mode Only)
t
RASP
60
100k
70
100k
80
100k
ns
Access Time from
OE
t
OEA
15
20
20
ns
OE
to Data Delay Time
t
OED
15
20
20
ns
OE
to Output High-Z
t
OEZ
3
20
3
20
3
20
ns
OE
Command Hold Time
t
OEH
15
20
20
ns
Data Output Hold after
CAS
low
t
DOH
5
5
5
ns
RAS
to Output High-Z
t
REZ
3
15
3
20
3
20
ns
WE
to Output High-Z
t
WEZ
3
15
3
20
3
20
ns
OE
to
CAS
Hold Time
t
OCH
5
5
5
ns
CAS
Hold Time to
OE
t
CHO
5
5
5
ns
OE
Precharge Time
t
OEP
5
5
5
ns
CAS
Set-Up Time for
CAS
-before-
RAS
Cycle
t
CSR
5
5
5
ns
CAS
Hold Time for
CAS
-before-
RAS
Cycle
t
CHR
10
15
15
ns
Transition Time
t
T
2
50
2
50
2
50
ns
Refresh Period
t
REF
16
16
16
ms
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
Notes:
1. Measure with a load equivalent to 1TTL inputs and 50 pF.
2. Assumes that t
RCD
t
RCD
(max.). If t
RCD
is greater than t
RCD
(max.), access time will be t
AA
dominant.
3. Assumes that t
RAD
t
RAD
(max.). If t
RAD
is greater than t
RCD
(max.), access time will be
controlled by t
CAC
.
4. Either t
RRH
or t
RCH
must be satisfied for a Read Cycle.
5. Access time is determined by the longest of t
AA
, t
CAC
and t
CPA
.
6. Assumes that t
RAD
t
RAD
(max.).
7. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.)
is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(max.)
limit, the access time is controlled by t
AA
and t
CAC
.
8. t
WCS
, t
RWD
, t
AWD
and t
CWD
are not restrictive operating parameters.
9. t
WCS
(min.) must be satisfied in an Early Write Cycle.
10. t
DS
and t
DH
are referenced to the latter occurrence of CAS of WE .
11.
t
T
is measured between V
IH
(min.) and V
IL
(max.). AC-measurements assume t
T
= 2 ns.
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
Read Cycle
ROW
ADDRESS
COLUMN
ADDRESS
DATA-OUT
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
RSH
t
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCH
t
RRH
t
AR
t
RCS
t
AA
t
OEA
t
CEZ
t
OEZ
t
CAC
t
CLZ
t
RAC
Don't Care
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
Early Write Cycle NOTE :
D
OUT
= Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
CWL
t
RWL
t
WCR
t
WCH
t
WP
t
WCS
t
AR
t
DS
t
DH
t
DHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Late Write Cycle ( OE Controlled Write)
NOTE : D
OUT
= Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
COLUMN
ADDRESS
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Fast Page Read Cycle
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G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
Fast Page Mode Late Write Cycle
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G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
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G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
Hidden Refresh Cycle ( Write )
NOTE : D
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=Open
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G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
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Write Cycle
Read-Modify-Write
t
CAH
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
PACKAGE
GLT440L08-60J4
60ns
Normal
EDO
SOJ 400mil 28L
GLT440L08-70J4
70ns
Normal
EDO
SOJ 400mil 28L
GLT440L08-80J4
80ns
Normal
EDO
SOJ 400mil 28L
Parts Numbers (Top Mark) Definition :
GLT 4 40 L 08 - 60 J4
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
G -LINK
GLT440L08
512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Oct 2001 (Rev.2.0)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 17 -
Package Information
400mil 28 Lead Small Outline J-form Package (SOJ)
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