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Datasheet: GLT44016-50J4 (G-Link Technology Corp.)

 

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G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
262,144 words by 16 bits organization.
Fast access time and cycle time.
Dual
CAS
Input.
Low power dissipation.
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
512 refresh cycles per 8ms.
Available in 40-Pin 400 mil SOJ and 40/44
Pin TSOP(II)
Single 5.0V
10% Power Supply.
All inputs and Outputs are TTL
compatible.
Extended Data-Out(EDO) Page Mode
operation.
The GLT44016 is a 262,144 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT44016 offers Fast
Page mode with Extended Data Output, and
has both BYTE WRITE and WORD WRITE
access cycles via two
CAS
pins. The
GLT44016 has symmetric address and
accepts 512-cycle refresh in 8ms interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 512 x 16 bits within a page, with cycle
times as short as 10ns.
The GLT44016 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE
25
28
30
35
40
50
Max.
RAS
Access Time, (t
RAC
)
25 ns 28 ns 30 ns 35 ns 40 ns 50 ns
Max. Column Address Access Time, (t
CAA
)
13 ns 13 ns 16 ns 18 ns 20 ns 25 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
10 ns 10 ns 12 ns 13 ns 15 ns 20 ns
Min. Read/Write Cycle Time, (t
RC
)
45 ns 45 ns 60 ns 65 ns 70 ns 85 ns
Max.
CAS
Access Time (t
CAC
)
8 ns
8 ns
10 ns 11 ns 12 ns 14 ns
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configuration :
Pin Descriptions:
Name
Function
A
0
- A
8
Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
DQ
1
- DQ
16
Data Inputs / Outputs
V
CC
+5V Power Supply
V
SS
Ground
NC
No Connection
GLT44016
SOJ Top View
TSOP(Type II)
Top View
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings*
Capacitance*
T
A
=25
C, V
CC
=5V
10%, V
SS
=0V
Operating Temperature, T
A
(ambient)
.......................................-0
C to +70
C
Storage Temperature(plastic)....-55
C to +150
C
Voltage Relative to V
SS
...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS
,
LCAS
,
UCAS
,
WE
,
OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note:Operation above Absolute Maximum Ratings can
abversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
CAS
means
UCAS
and
LCAS
.
l
All voltages are referenced to GND.
l
After power up, wait more than 100
s and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
512
OE
CLOCK
GENERATOR
W E
CLOCK
GENERATOR
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
Data I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O
BUFFER
MEMORY
ARRAY
REFRESH
COUNTER
.
.
X
0
- x
8
512 16
Y
0
- Y
8
9
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
OE
WE
RAS
UCAS
V
CC
V
SS
A
0
A
1
A
7
A
8
ADDRESS BUFFERS
AND PREDECODERS
ROW
DECODERS
LCAS
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
Truth Table: GLT44016
Function
RAS
CASL CASH WE
OE ADDRESS
DQs
Notes
Stanby
H
H
X
H
X
X
X
High-Z
Read: Word
L
L
L
H
L
ROW/COL Data Out
Read: Lower Byte
L
L
H
H
L
ROW/COL Lower Byte,Data-Out
Upper Byte,High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL Lower Byte,High-Z
Upper Byte,Data-Out
Write: Word(Early
Write)
L
L
L
L
X
ROW/COL Data-In
Write: Lower Byte
(Early)
L
L
H
L
X
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
Write: Upper Byte
(Early)
L
H
L
L
X
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
Read Write
L
L
L
H
L
L
H
ROW/COL Data-Out,Data-In
1,2
EDO-Page-
Mode Read
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
L
H
L
H
H
L
L
ROW/COL
COL
Data-Out
Data-Out
1
1
EDO-Page-
Mode Write
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
L
H
L
L
L
X
X
ROW/COL
COL
Data-In
Data-In
2
2
EDO-Page-
Mode Read-
Write
1st Cycle
2nd Cycle
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
ROW/COL
COL
Data-Out,Data-In
Data-Out,Data-In
1,2
1,2
Hidden
Refresh
Read
Write
L
H
L
L
H
L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
Data-Out
Data-In
1
2,3
RAS
-Only Refresh
L
H
H
X
X
ROW
High-Z
CBR Refresh
H
L
L
L
X
X
High-Z
4
Notes:
1. These READ cycles may also be BYTE READ cycles (either
UCAS
or
LCAS
active).
2. These WRITE cycles may also be BYTE READ cycles (either
UCAS
or
LCAS
active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (
UCAS
or
LCAS
).
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, V
CC
=5V
10%, V
SS
=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max. Unit Notes
I
LI
Input Leakage Current
(any input pin)
0V
V
IN
5.5V
(All other pins not under
test=0V)
-10
+10
A
I
LO
Output Leakage Current
(for High-Z State)
0V
V
out
5.5V
Output is disabled (Hiz)
-10
+10
A
I
CC1
Operating Current,
Random READ/WRITE
t
RC
= t
RC
(min.)
t
RAC
= 25ns
t
RAC
= 28ns
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
270
270
250
210
190
170
mA
1,2
I
CC2
Standby Current,(TTL)
RAS
,
UCAS
,
LCAS
at V
IH
other inputs
V
SS
4
mA
I
CC3
Refresh Current,
RAS
-Only
RAS
cycling,
UCAS
,
LCAS
at V
IH
t
RC
= t
RC
(min.)
t
RAC
= 25ns
t
RAC
= 28ns
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
270
270
250
210
190
170
mA
2
I
CC4
Operating Current,
EDO Page Mode
RAS
at V
IL
,
UCAS
,
LCAS
address cycling:t
PC
=t
PC
(min.)
t
RAC
= 25ns
t
RAC
= 28ns
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
270
270
250
210
190
170
mA
1,2
I
CC5
Refresh Current,
CAS
Before
RAS
RAS
,
UCAS
,
LCAS
address cycling:
t
RC
=t
RC
(min.)
t
RAC
= 25ns
t
RAC
= 28ns
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
270
270
250
210
190
170
mA
1
I
CC6
Standby Current, (CMOS)
RAS
V
CC
-0.2V,
UCAS
V
CC
-0.2V,
LCAS
V
CC
-0.2V,
All other inputs V
SS
2
mA
V
IL
Input Low Voltage
-1
+0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+1
V
3
V
OL
Output Low Voltage
I
OL
= 4.2mA
0.4
V
V
OH
Output High Voltage
I
OH
= -5.0mA
2.4
V
Notes:
1.I
CC
is dependent on output loading when the device output is selected. Specified I
CC
(max.) is measured with the output open.
2.I
CC
is dependent upon the number of address transitions specified I
CC
(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and EDO Fast Page Mode.
3.Specified V
IL
(min.) is steady state operation. During transitions V
IL
(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC
parameters are measured with V
IL
(min.)
V
SS
and V
IH
(max.)
V
CC
.
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
AC Characteristics
T
A
= 0
C to 70
C , V
CC
= 5 V
10
%
, VIH/VIL = 2.4/0.8 V, V
OH
/V
OL
= 2.0/0.8V
An initial pause of 100
s and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up.
25
28
30
35
40
50
Parameter
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time
t
RC
45
45
60
65
70
85
ns
Read Modify Write Cycle Time
t
RWC
67
67
79
86
91
106
ns
RAS
Precharge Time
t
RP
15
15
25
25
25
30
ns
RAS
Pulse Width
t
RAS
25
100k
28
100k
30
100k
35
100k
40
100k
50
100k ns
Access Time from
RAS
t
RAC
25
28
30
35
40
50
ns
1,2,3
Access Time from
CAS
t
CAC
8
8
10
11
12
14
ns 1,5,10
Access Time from Column Address
t
AA
13
13
16
18
20
25
ns
1,5,6
CAS
to Output Low-Z
t
CLZ
0
0
0
0
0
0
ns
CAS
to Output High-Z
t
CEZ
0
5
0
5
3
7
3
8
3
8
3
8
ns
RAS
Hold Time
t
RSH
7
7
7
8
8
8
ns
RAS
Hold Time Referenced to
OE
t
ROH
4
4
7
8
8
8
ns
CAS
Hold Time
t
CSH
25
25
25
30
35
42
ns
CAS
Pulse Width
t
CAS
4
4
4.5
5
6
8
ns
RAS
to CAS Delay Time
t
RCD
10
17
10
17
10
20
11
24
12
28
13
36
ns
RAS
to Column Address Delay Time
t
RAD
8
12
8
12
8
14
9
17
10
20
11
25
ns
7
CAS
to RAS Precharge Time
t
CRP
5
5
5
5
5
5
ns
Row Address Set-Up Time
t
ASR
0
0
0
0
0
0
ns
Row Address Hold Time
t
RAH
4
4
6
7
8
9
ns
Column Address Set-Up Time
t
ASC
0
0
0
0
0
0
ns
Column Address Hold Time
t
CAH
4
4
5
6
6
7
ns
Column Address to RAS Lead Time
t
RAL
13
13
16
18
20
25
ns
Column Address Hold Time Referenced to
RAS
t
AR
19
19
25
30
34
35
ns
Read Command Set-Up Time
t
RCS
0
0
0
0
0
0
ns
Read Command Hold Time Referenced to
CAS
t
RCH
0
0
0
0
0
0
ns
4
Read Command Hold Time Referenced to
RAS
t
RRH
0
0
0
0
0
0
ns
4
Write Command Set-Up Time
t
WCS
0
0
0
0
0
0
ns
8,9
Write Command Hold Time
t
WCH
4
4
5
6
6
6
ns
Write Command Pulse Width
t
WP
4
4
5
6
6
6
ns
Write Command to
RAS
Lead Time
t
RWL
7
7
7
8
8
8
ns
Write Command to
CAS
Lead Time
t
CWL
5
5
6
7
7
7
ns
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
AC Characteristics
25
28
30
35
40
50
Parameter
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Data Set-Up Time
t
DS
0
0
0
0
0
0
0
0
ns
Data Hold Time
t
DH
4
4
7
8
8
8
ns
Data Hold Time Referenced to
RAS
t
DHR
19
19
27
32
36
37
ns
RAS
to
WE
E Delay Time
t
RWD
36
36
43
49
54
64
ns
CAS
to
WE
Delay Time
t
CWD
19
19
21
23
24
26
ns
Column Address to
WE
Delay Time
t
AWD
24
24
27
30
32
37
ns
RAS
to
CAS
Precharge Time
t
RPC
0
0
0
0
0
0
ns
Access Time from
CAS
Precharge
t
CPA
15
15
18
20
22
27
ns
EDO Page Mode Cycle Time
t
PC
10
10
12
13
15
20
ns
EDO Page Mode Read-Modify-Write Cycle Time
t
PRWC
35
35
39
43
45
50
ns
CAS
Precharge Time (EDO Page Mode)
t
CP
3
3
4.5
5
6
8
ns
RAS
Pulse Width (EDO Page Mode Only)
t
RASP
25
100k
28
100k
30
100K
35
100k
40
100k
50
100k ns
Access Time from
OE
t
OEA
8
8
10
11
12
14
ns
OE
to Data Delay Time
t
OED
5
5
7
8
8
8
ns
OE
to Output High-Z
t
OEZ
3
7
3
7
3
7
3
8
3
8
0
8
ns
OE
Command Hold Time
t
OEH
5
5
6
6
7
7
ns
Data Output Hold after
CAS
low
t
DOH
4
4
5
5
5
5
ns
RAS
to Output High-Z
t
REZ
3
7
3
7
3
7
3
8
3
8
3
8
ns
WE
to Output High-Z
t
WEZ
3
10
3
10
3
10
3
10
3
10
3
12
ns
OE
to
CAS
Hold Time
t
OCH
8
8
8
8
8
8
ns
CAS
Hold Time to
OE
t
CHO
8
8
8
8
8
8
ns
OE
Precharge Time
t
OEP
8
8
8
8
8
8
ns
CAS
Set-Up Time for
CAS
-before-
RAS
Cycle
t
CSR
5
5
10
10
10
10
ns
CAS
Hold Time for
CAS
-before-
RAS
Cycle
t
CHR
6
6
7
8
8
10
ns
Transition Time
t
T
1.5
50
1.5
50
1.5
50
1.5
50
1.5
50
2
50
ns
Refresh Period
t
REF
8
8
8
8
8
8
ms
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
Notes:
1. Measure with a load equivalent to one TTL inputs and 50 pF.
2. Assumes that t
RCD
t
RCD
(max.). If t
RCD
is greater than t
RCD
(max.), access time will be t
AA
dominant.
3. Assumes that t
RAD
t
RAD
(max.). If t
RAD
is greater than t
RCD
(max.), access time will be
controlled by t
CAC
.
4. Either t
RRH
or t
RCH
must be satisfied for a Read Cycle.
5. Access time is determined by the longest of t
CAA
, t
CAC
and t
CPA
.
6. Assumes that t
RAD
t
RAD
(max.).
7. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.)
is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(max.)
limit, the access time is controlled by t
CAA
and t
CAC
.
8. t
WCS
, t
RWD
, t
AWD
and t
CWD
are not restrictive operating parameters.
9. t
WCS
(min.) must be satisfied in an Early Write Cycle.
10. t
DS
and t
DH
are referenced to the latter occurrence of
CAS
of
WE
.
t
T
is measured between V
IH
(min.) and V
IL
(max.). AC-measurements assume t
T
= 1.5 ns.
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
Read Cycle
ROW
ADDRESS
COLUMN
ADDRESS
DATA-OUT
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
RSH
t
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCH
t
RRH
t
AR
t
RCS
t
AA
t
OEA
t
CEZ
t
OEZ
t
CAC
t
CLZ
t
RAC
Don't Care
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
Early Write Cycle NOTE :
D
OUT
= Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
CWL
t
RWL
t
WCR
t
WCH
t
WP
t
WCS
t
AR
t
DS
t
DH
t
DHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Late Write Cycle ( OE Controlled Write)
NOTE : D
OUT
= Open
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
COLUMN
ADDRESS
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Fast Page Read Cycle
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Don't Care
t
RCS
t
RCH
t
RCS
t
RCS
t
RCH
t
RRH
t
OEA
t
CAC
t
OEA
t
CAC
t
CLZ
t
RAC
t
AA
t
OEZ
t
OFF
t
AA
t
CLZ
t
OEZ
t
OEZ
t
OFF
t
OFF
t
CLZ
t
AA
VALID
DATA-UOT
VALID
DATA-UOT
VALID
DATA-UOT
Fast Page Write Cycle
NOTE : D
OUT
= Open
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
PC
t
RSH
t
ASR
t
RAD
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
ASC
t
CAH
t
CAH
t
WCS
t
WP
t
WCH
t
WCS
t
WCS
t
WCH
t
WCH
t
WP
t
WP
t
DS
t
DS
t
DS
t
DH
t
DS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
t
CWL
t
CWL
t
CWL
t
RWL
t
RHCP
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
Fast Page Mode Late Write Cycle
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
CAS
t
CAS
t
CP
t
CP
t
PC
t
RSH
t
ASC
t
ASC
t
CAH
t
CAH
t
DS
t
DS
t
DH
t
DS
t
DH
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
Don't Care
t
CSH
t
RHCP
t
CRP
VALID
DATA-IN
VALID
DATA-IN
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
RCS
t
WP
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RCS
t
RCS
t
RWL
t
OEH
t
OEH
t
OEH
t
OED
t
OED
t
DH
t
OED
Hi-Z
Hi-Z
Hi-Z
Fast Page Read - Modify - Write Cycle
t
RASP
t
RP
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
Don't Care
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
PRWC
t
RCS
t
WP
t
CWL
t
WP
t
CWL
t
RWL
t
CWD
t
AWD
t
RWD
t
OEA
t
CWD
t
AWD
t
CPWD
t
OEA
t
OEH
t
RAC
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
CLZ
t
CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR.
COL.
ADDR.
COL.
ADDR.
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
CAS Before RAS Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
CSR
t
CSR
t
CHR
t
CHR
t
RPC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
RAS -Only Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
CRP
t
ASR
t
ASR
t
RAH
t
RAH
ROW
ROW
Address
V
IH-
V
IL-
Hidden Refresh Cycle ( Read )
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RAC
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
CAC
t
RCS
t
ASC
t
CAH
t
ASR
t
CAH
t
RAD
t
RAL
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
t
RC
t
WHR
t
AA
t
OEA
t
CLZ
t
OFF
t
OEZ
DATA-OUT
OPEN
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
Hidden Refresh Cycle ( Write )
NOTE : D
OUT
=Open
t
RP
t
CRP
t
RCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
DS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
t
RP
t
DH
t
WP
t
WCH
t
WCS
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
RSH
t
CHR
t
RC
t
RAS
t
RAS
COLUMN
ADDRESS
DATA-IN
t
RC
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
CAS - Before RAS Refresh Counter Test Cycle
t
CAS
t
CPT
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
t
RP
t
RAS
t
CSR
t
CHR
t
RSH
t
RAL
t
ASC
t
AA
t
CAC
t
RCS
t
RRH
t
RCH
t
WRP
t
WRH
t
WRH
t
WRP
t
OEA
t
CEZ
t
OEZ
t
CLZ
t
RWL
t
CWL
t
WCH
t
WCS
t
WP
t
DS
t
DH
t
RCS
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
DH
t
DS
t
OED
t
OEZ
t
CLZ
t
CAC
t
AA
t
OEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
OH-
V
OL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
t
CAH
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
PACKAGE
GLT44016-25J4
25ns
Normal
EDO
40L 400mil SOJ
GLT44016-28J4
28ns
Normal
EDO
40L 400mil SOJ
GLT44016-30J4
30ns
Normal
EDO
40L 400mil SOJ
GLT44016-35J4
35ns
Normal
EDO
40L 400mil SOJ
GLT44016-40J4
40ns
Normal
EDO
40L 400mil SOJ
GLT44016-50J4
50ns
Normal
EDO
40L 400mil SOJ
GLT44016-25TC
25ns
Normal
EDO
44L 400mil TSOP
GLT44016-28TC
28ns
Normal
EDO
44L 400mil TSOP
GLT44016-30TC
30ns
Normal
EDO
44L 400mil TSOP
GLT44016-35TC
35ns
Normal
EDO
44L 400mil TSOP
GLT44016-40TC
40ns
Normal
EDO
44L 400mil TSOP
GLT44016-50TC
50ns
Normal
EDO
44L 400mil TSOP
Parts Numbers (Top Mark) Definition :
GLT 4 40 16 - 40 J4
Note : C
CDROM , H
HDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
25 : 25ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
G -LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 17 -
Package Information
40/44 Lead Thin Small Outline Package SOJ
40/44 Lead Thin Small Outline Package TSOP(Type II)
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