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Datasheet: GLT4161L16-50J4 (G-Link Technology Corp.)

 

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G -LINK
GLT4161L16
1M X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2002 (Rev.2.1)
G-Link Technology Corporation
1759 S. Main St., Suite 128
Milpitas, CA 95035 U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD. IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 1 -
Features :
Description :
1,048,576
words by 16 bits organization.
Fast access time and cycle time.
Dual
CAS
Input.
Low power dissipation.
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh.
1024 refresh cycles per 16ms.
Available in 400 mil SOJ / TSOPII
Packages.
Single 3.3V
0.3V Power Supply.
I
nputs and Outputs are TTL compatible.
Fast Page Mode operation.
Self refresh capability (S-Version)
The GLT4161L16 is a 1,048,576 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT4161L16 offers
Fast Page mode and has both BYTE WRITE
and WORD WRITE access cycles via two
CAS
pins. The GLT4161L16 has symmetric
address and accepts 1024-cycle refresh in
16ms interval.
All inputs are TTL compatible. Fast
Page Mode operation allows random access
up to 1024 x 16 bits within a page, with cycle
times as short as 23ns.
HIGH PERFORMANCE
40
45
50
70
Max.
RAS
Access Time, (t
RAC
)
40 ns
45 ns
50 ns
70 ns
Max. Column Address Access Time, (t
CAA
)
20 ns
22 ns
25 ns
35 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
23 ns
25 ns
28 ns
30 ns
Min. Read/Write Cycle Time, (t
RC
)
75 ns
80 ns
90 ns 124 ns
Max.
CAS
Access Time (t
CAC
)
12 ns
12 ns
15 ns
20 ns
G -LINK
GLT4161L16
1M X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2002 (Rev.2.1)
G-Link Technology Corporation
1759 S. Main St., Suite 128
Milpitas, CA 95035 U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD. IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 2 -
Pin Configuration :
Vcc
DQ
0
A0
A1
1
2
3
4
5
6
7
9
10
11
12
13
NC
OE
LCAS
V
SS
DQ
15
DQ
1
WE
RAS
NC
A
9
A
8
8
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ
2
DQ
3
Vcc
DQ
4
DQ
5
DQ
6
DQ
7
NC
A2
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
UCAS
A
7
A
6
A
5
SOJ Top View
V
CC
21
V
SS
22
NC
NC
A3
A
4
Vcc
DQ
0
A0
A1
1
2
3
4
5
6
7
9
10
12
13
14
NC
OE
LCAS
V
SS
DQ
15
DQ
1
WE
RAS
NC
A
9
A
8
8
15
16
17
18
19
20
21
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
DQ
2
DQ
3
Vcc
DQ
4
DQ
5
DQ
6
DQ
7
NC
A2
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
UCAS
A
7
A
6
A
5
TSOP(Type II)
Top View
V
CC
22
23
V
SS
34
11
NC
NC
NC
A3
NC
A
4
Pin Descriptions:
Name
Function
A
0
- A
9
Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
DQ
0
- DQ
15
Data Inputs / Outputs
V
CC
+3.3V Power Supply
V
SS
Ground
NC
No Connection
G -LINK
GLT4161L16
1M X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2002 (Rev.2.1)
G-Link Technology Corporation
1759 S. Main St., Suite 128
Milpitas, CA 95035 U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD. IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 3 -
Absolute Maximum Ratings*
Capacitance*
T
A
=25
C, V
CC
=3.3V
0.3V, V
SS
=0V
Operating Temperature, T
A
(ambient)
........................................0
C to +70
C
Storage Temperature(plastic)....-55
C to +150
C
Voltage Relative to V
SS
...............-1.0V to + 4.6V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS
,
LCAS
,
UCAS
,
WE
,
OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note:Operation above Absolute Maximum Ratings can
abversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
CAS
means
UCAS
and
LCAS
.
l
All voltages are referenced to GND.
l
After power up, wait more than 100
s and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
Memory
Array
1024X1024X16
Upper
Byte
Control
Sense Amplifier
Column Decoder
Row
Address
Buffer
Column
Address
Buffer
...1024X16...
...1024...
....1024....
Lower
Byte
Control
Row Decoder
Data
Output
Buffer
Data
Input
Buffer
Data
Output
Buffer
Data
Input
Buffer
CAS before
RAS Counter
Clock
Generator
A0
|
A9
X0..X9
Y0..Y9
DQ8
|
DQ15
DQ0
|
DQ7
RAS
LCAS
UCAS
WE
Vcc
GND
OE
X8
X8
X8
X8
X8
X1
6
X8
X8
X8
G -LINK
GLT4161L16
1M X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2002 (Rev.2.1)
G-Link Technology Corporation
1759 S. Main St., Suite 128
Milpitas, CA 95035 U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD. IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 4 -
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, V
CC
=3.3V
0.3V, V
SS
=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max.
Unit
Notes
I
LI
Input Leakage Current
(any input pin)
0V
V
IN
Vcc+0.3V
(All other pins not under test=0V)
-5
+5
A
I
LO
Output Leakage
Current
(for High-Z State)
0V
V
out
Vcc
Output is disabled (Hiz)
-5
+5
A
I
CC1
Operating Current,
Random READ/WRITE
t
RC
= t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 70ns
160
150
140
130
mA
1,2
I
CC2
Standby Current,(TTL)
RAS , UCAS , LCAS at V
IH
other inputs
V
SS
1
mA
I
CC3
Refresh Current,
RAS -Only
RAS cycling, UCAS , LCAS at
V
IH
t
RC
= t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 70ns
160
150
140
130
mA
2
I
CC4
Operating Current,
FAST Page Mode
RAS at V
IL
, UCAS , LCAS
address cycling:t
PC
=t
PC
(min.)
t
RAC
= 40ns
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 70ns
160
150
140
130
mA
1,2
I
CC5
Refresh Current,
CAS Before RAS
RAS , UCAS , LCAS
address cycling:
t
RC
=t
RC
(min.)
t
RAC
= 40ns
t
RAC
= 45ns
t
RAC
= 50ns
t
RAC
= 70ns
160
150
140
130
mA
1
I
CC6
Standby Current,
(CMOS)
RAS
V
CC
-0.2V, UCAS
V
CC
-0.2V,
LCAS
V
CC
-0.2V,
All other inputs V
SS
300
A
1,5
I
CC7
Self Refresh Current
RAS = UCAS = LCAS =V
IL
WE = OE =A
0
~A
9
=V
CC
-0.2V or
0.2V
DQ
0
~DQ
15
=V
CC
-0.2V,0.2V or
Open
300
A
V
IL
Input Low Voltage
-0.3
+0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
4
V
OL
Output Low Voltage
I
OL
= 2mA
0.4
V
V
OH
Output High Voltage
I
OH
= -2mA
2.4
V
Notes:
1.I
CC
is dependent on output loading when the device output is selected. Specified I
CC
(max.) is measured with the output open.
2.I
CC
is dependent upon the number of address transitions specified I
CC
(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and Fast Page Mode.
3.Specified V
IL
(min.) is steady state operation. During transitions V
IL
(min.) may undershoot to -1.0V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)
V
SS
and V
IH
(max.)
V
CC
.
3.Specified V
IH
(max.) is steady state operation. During transitions V
IH
(max.) may undershoot to +1.0V for a period not to exceed 15ns. All AC
parameters are measured with V
IL
(min.)
V
SS
and V
IH
(max.)
V
CC
.
5.S-Veraion
G -LINK
GLT4161L16
1M X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Oct 2002 (Rev.2.1)
G-Link Technology Corporation
1759 S. Main St., Suite 128
Milpitas, CA 95035 U.S.A.
G-Link Technology Corporation,Taiwan
6F, NO. 24-2, INDUSTRY E RD. IV, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R. O. C.
- 5 -
AC Characteristics
T
A
= 0
C to 70
C , V
CC
= 3.3V
0.3V, V
IH
/ V
IL
= 3.0/0 V, V
OH
/V
OL
= 2.0/0.8V
An initial pause of 100
s and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
40
45
50
70
Parameter
Symbol
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time
t
RC
75
80
90
124
ns
Read Modify Write Cycle Time
t
RWC
110
110
130
170
ns
RAS
Precharge Time
t
RP
25
25
30
50
ns
RAS
Pulse Width
t
RAS
40
100K
45
100k
50
100K
70
10k
ns
Access Time from
RAS
t
RAC
40
45
50
70
ns
3, 4
Access Time from
CAS
t
CAC
12
12
15
20
ns
3, 4
Access Time from Column Address
t
AA
20
22
25
35
ns
3, 4
CAS
to Output Low-Z
t
CLZ
0
0
0
3
ns
3
RAS
Hold Time
t
RSH
12
13
15
20
ns
CAS
Hold Time
t
CSH
40
46
50
50
ns
CAS
Pulse Width
t
CAS
12
10k
13
10k
15
10k
15
10k
ns
RAS
to CAS Delay Time
t
RCD
17
28
18
33
19
36
20
50
ns
RAS
to Column Address Delay Time
t
RAD
12
20
13
23
15
26
15
35
ns
7
CAS
to RAS Precharge Time
t
CRP
5
5
5
5
ns
Row Address Set-Up Time
t
ASR
0
0
0
0
ns
Row Address Hold Time
t
RAH
7
8
9
10
ns
Column Address Set-Up Time
t
ASC
0
0
0
0
ns
Column Address Hold Time
t
CAH
5
6
7
15
ns
Column Address to RAS Lead Time
t
RAL
20
23
25
35
ns
Column Address Hold Time Referenced to
RAS
t
AR
30
39
40
50
ns
Read Command Set-Up Time
t
RCS
0
0
0
0
ns
Read Command Hold Time Referenced to
CAS
t
RCH
0
0
0
0
ns
4
Read Command Hold Time Referenced to
RAS
t
RRH
0
0
0
0
ns
4
Write Command Set-Up Time
t
WCS
0
0
0
0
ns
8,9
Write Command Hold Time
t
WCH
5
6
7
15
ns
Write Command Pulse Width
t
WP
5
6
7
15
ns
Write Command to
RAS
Lead Time
t
RWL
12
12
15
30
ns
Write Command to
CAS
Lead Time
t
CWL
12
12
15
15
ns
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