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Datasheet: gm7030-H (Genesis Microchip Inc.)

 

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Genesis Microchip Inc.
2150 Gold Street, P.O. Box 2150, Alviso, CA USA 95002, Tel 408-262-6599, Fax 408-262-6365
165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8, Tel 905-889-5400, Fax 905-889-5422
George Thangiah Complex(E), 2nd Flr, 80 Feet Road, Jeevan Bhima Nagar, Bangalore 560 075, India, Tel 91-80-526 3878, Fax 91-80-529 6245
4F, No. 57, Sing Jung Road, NeiHu Taipei, Taiwan 114, R.O.C, Tel 886-2-2791-0118, Fax 886-2-2791-0196
143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090, Tel 82-2-553-5693, Fax 82-2-552-4942
Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guangdong, P.R.C., Tel 86-755-83860101, Fax 86-755-83867874
#310-311 Century Financial Tower, No. 1, Su Hua Road, Suzhou Industrial Park, Suzhou, Jiangsu Province, P.R.C., 215021 Tel 86-512-67620380, Fax 86-512-67620385
2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759
www.genesis-microchip.com / info@genesis-microchip.com
Genesis Microchip Publication
Preliminary Data Sheet
gm7030/gm7030-H
Sections in this document and all other related documentation that mention HDCP refer only
to the HDCP-enabled chip version (gm7030-H). All other sections apply to both chip versions
(gm7030 and gm7030-H).
Publication number: C7030-DAT-01F
Publication date: February 2003
gm7030/gm7030-H Preliminary Data Sheet
Revision History
Document Change
Release
Date
C7030-DAT-01B
Initial Release
February 2001
C7030-DAT-01C
Corrected pin 89 description. Updated package drawing and
updated feature descriptions
April 2001
C7030-DAT-01D
Changed names and provided greater description where needed
of following pins. These changes affect Figure 2 and Table 10.
- 8 (formerly AGND) to VSS
- 9 (formerly AVDD_2.5) to DVDD_2.5
- 35 (formerly DVI_SCL) to DVI_DDC_SCL
- 36 (formerly DVI_SDA) to DVI_DDC_SDA
- 66 (formerly AVDD_2.5) to DVDD_2.5
- 69 (formerly AVDD_2.5) to DVDD_2.5
- 70 (formerly AGND) to VSS
- 71 (formerly AVDD_2.5) to DVDD_2.5
- 72 (formerly AGND) to VSS
- 93 (formerly VSS) to DVDD_2.5
- 98 (formerly AVDD_3.3) to DVDD_3.3
- 99 (formerly AGND) to VSS
- 110 (formerly DVDD_3.3) to DVDD_2.5
Modified section 5.13.1.
Changed resistor values in Figure 5.
Modified Table 21 and Table 22.
Modified Figure 4.
In last sentence of section 5.13.1.1, changed 0x8F to 0x7F.
October 2001
C7030-DAT-01E
Corrected pin 141, pin 142 descriptions
October 2002
C7030-DAT-01F
Added Thermal Resistance information to section 6, table 21.
February 2003
The following are Trademarks or Registered trademarks of Genesis Microchip Inc.:
Genesis
TM
Genesis Display Perfection
TM
ESM
TM
RealColor
TM
Ultra-Reliable
DVI
TM
Real
Recovery
TM
Sage
TM
Smartset
TM
Jag-ASM
TM
SureSync
TM
Intelligent Picture ProcessingTM
Adaptive Contrast ControlTM
Adaptive Backlight ControlTM
Faroudja
TM
DCDi
TM
TrueLife
TM
IntelliComb
TM
Copyright 2003, Genesis Microchip Inc. All Rights Reserved.
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It
is the customer's responsibility to obtain the most recent revision of the document. Genesis Microchip Inc. makes
no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in
this document.
gm7030/gm7030-H Preliminary Data Sheet
C7030-DAT-01F
February
2003
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
i
Table Of Contents
1. IMPORTANT NOTE...................................................................................................................1
2. Overview......................................................................................................................................2
3. Pinout Description........................................................................................................................3
4. Theory of Operation...................................................................................................................10
5. Functional Description...............................................................................................................11
5.1
Reset ..............................................................................................................................11
5.2
Clock Domains/Generation ...........................................................................................11
5.2.1
TCLK ........................................................................................................................12
5.2.2
RCLK (DDS Reference Clock).................................................................................12
5.2.3
SCLK (Source Clock) ...............................................................................................12
5.2.3.1 Analog...............................................................................................................12
5.2.3.2 Digital ...............................................................................................................12
5.2.3.3
Test Pattern Generator ......................................................................................13
5.2.3.4
No Input Stand Alone ....................................................................................13
5.2.4
DCLK (Display Clock) .............................................................................................13
5.3
Analog Input - Analog to Digital Converter (ADC) .....................................................13
5.3.1
Sync Signal Support ..................................................................................................13
5.3.2
Pin Connection ..........................................................................................................15
5.3.3
ADC Characteristics..................................................................................................17
5.3.4
Clock Recovery Circuit .............................................................................................17
5.3.5
Sampling Phase Adjustment......................................................................................18
5.3.6
ADC Capture Window ..............................................................................................18
5.3.6.1
Image Data Capture Interface ...........................................................................19
5.4
Digital Input - Ultra-Reliable DVI Receiver.................................................................20
5.4.1
Ultra-Reliable DVI Receiver Characteristics ............................................................20
5.4.2
Digital Input Capture Window ..................................................................................21
5.4.3
HDCP (High-Bandwidth Digital Content Protection)...............................................21
5.5
Input Format Measurement ...........................................................................................21
5.5.1
Measurement .............................................................................................................22
5.5.2
Format Change Detection..........................................................................................22
5.5.2.1 IRQ
controller ...................................................................................................22
5.5.3
Input Timing Watchdog ............................................................................................23
5.6
Input Pixel Measurement...............................................................................................23
5.6.1
Image Phase Measurement........................................................................................23
5.6.2
Image Boundary Detection........................................................................................23
5.6.3
Image Auto Balance ..................................................................................................23
gm7030/gm7030-H Preliminary Data Sheet
C7030-DAT-01F
February
2003
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
ii
5.7
Digital Color Controls...................................................................................................23
5.7.1
Color Controls Overview ..........................................................................................24
5.7.2
YUV Hue / Saturation Controls ................................................................................24
5.7.3
RealColor Flesh tone Adjustment .............................................................................25
5.8
SmartSCAN Line Rate Adjuster ...................................................................................25
5.9
Gamma Correction ........................................................................................................25
5.10
Output - 10-bit DAC .....................................................................................................26
5.10.1
Sync Insertion............................................................................................................26
5.10.2
Pedestal......................................................................................................................26
5.10.3
Programming the Display Timing.............................................................................29
5.10.4
Sync Drop Protection ................................................................................................30
5.11
OSD (On-Screen Display).............................................................................................33
5.11.1
On-Chip OSD............................................................................................................33
5.12
Multi-Function Bus (MFB) ...........................................................................................34
5.13
Host Interface ................................................................................................................35
5.13.1
Two Wire Serial Interface .........................................................................................35
5.13.1.1 Device
Addressing ...........................................................................................36
5.13.1.2 Read/Write
Operations .....................................................................................36
5.13.1.3 Continuous
Read/Write
Operations..................................................................37
5.13.1.4 Page
Access......................................................................................................38
5.13.2
Proprietary Serial Interface .......................................................................................39
5.13.2.1 Serial Communication Protocol .......................................................................40
6. Electrical Characteristics............................................................................................................44
7. Mechanical Specifications .........................................................................................................45
8. Ordering Information .................................................................................................................46
gm7030/gm7030-H Preliminary Data Sheet
C7030-DAT-01F
February
2003
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
iii
List of Figures
Figure 1: gm7030 Block Diagram .............................................................................................2
Figure 2: gm7030 Pinout ...........................................................................................................3
Figure 3: Clock Domains.........................................................................................................11
Figure 4: CSync Signal Types .................................................................................................14
Figure 5: Example Analog Input Signal Terminations ............................................................15
Figure 6: Analog Input Clock Recovery..................................................................................18
Figure 7: Analog Input Capture Window ................................................................................19
Figure 8: RGB and YUV Color Controls ................................................................................24
Figure 9: Black Level, Contrast & Brightness Transfer Function ...........................................25
Figure 10: DAC Output Timing...............................................................................................26
Figure 11: DAC Output Waveform, Sync, No Pedestal ..........................................................26
Figure 12: DAC Output Waveform, Sync & Pedestal.............................................................27
Figure 13: Display Windows & Timing ..................................................................................30
Figure 14: Watchdog Programmable Window ........................................................................31
Figure 15: Watchdog Timing Example 1.................................................................................31
Figure 16: Watchdog Timing Example 2.................................................................................32
Figure 17: Watchdog Timing Example 3.................................................................................32
Figure 18: HS_OUT Width Protection ....................................................................................32
Figure 19: On-Chip OSD Window Location...........................................................................34
Figure 20: Two Wire Protocol Byte Construction...................................................................35
Figure 21: Write Operation......................................................................................................37
Figure 22: Read Operation.......................................................................................................37
Figure 23: Continuous Write ...................................................................................................38
Figure 24: Continuous Read ....................................................................................................38
Figure 25: 1-bit Bit Order ........................................................................................................40
Figure 26: 4-bit Bit Order ........................................................................................................40
Figure 27: Communication Protocol Overview.......................................................................41
Figure 28: Burst Mode.............................................................................................................41
Figure 29: Write Timing Diagram ...........................................................................................42
Figure 30: Read Timing Diagram............................................................................................42
Figure 31: 144-pin PQFP.........................................................................................................45
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