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Datasheet: gm5060 (Genesis Microchip Inc.)

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Genesis Microchip Inc.
165 Commerce Valley Dr. West
Thornhill ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422
2150 Gold Street
PO Box 2150 Alviso CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365
4F, No. 24, Ln 123, Sec 6, Min-Chung E. Rd.
Taipei Taiwan Tel: (2) 2791-0118 Fax: (2) 2791-0196
143-37 Hyundai Tower
Unit 902 Samsung-dong Kangnam-gu Seoul Korea 135-090 Tel: (82-2) 553-5693 Fax: (82-2) 552-4942
www.genesis-microchip.com / info@genesis-microchip.com
Genesis Microchip Publication
DATA SHEET
gm5060/gm5060-H

Sections in this document and all other related documentation that mention HDCP refer
only to the gm5060-H (HDCP-enabled) chip. All other sections apply to both the gm5060-H
chip and the gm5060 (non-HDCP) chip.
Publication number: C5060-DAT-01G
Publication date: February 2002
Genesis Microchip
gm5060 / gm5060-H Data Sheet




























Trademarks: RealColor and Ultra-Reliable DVI are trademarks of Genesis Microchip Inc.
Copyright 2002, Genesis Microchip Inc. All Rights Reserved.
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without
notice. It is the customer's responsibility to obtain the most recent revision of the document. Genesis
Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors
or omissions that may appear in this document.
Genesis Microchip
gm5060/gm5060-H Data Sheet
February 2002
C5060-DAT-01G
iii
Document history
Previous publication releases:
C5060-DAT-01A January
2001
C5060-DAT-01B February
2001
C5060-DAT-01C April
2001
C5060-DAT-01D April
2001
C5060-DAT-01E July
2001
C5060-DAT-01F November
2001
Current publication releases:
C5060-DAT-01G Initial release
February 2002

Genesis Microchip
gm5060/gm5060-H Data Sheet
February 2002
C5060-DAT-01G
iv
Table Of Contents
1. Overview ................................................................................................................................... 1
1.1 gm5060 System Design Example....................................................................................... 2
1.2 gm5060/gm5060-H Features.............................................................................................. 3
2. Pinout Diagram ......................................................................................................................... 4
3. Pin List ...................................................................................................................................... 6
4. Functional Description............................................................................................................. 12
4.1 Clocking Options............................................................................................................... 13
4.1.1 TCLK Requirements............................................................................................... 13
4.1.2 Synthesized Clocks ................................................................................................ 16
4.2 Hardware and Software Resets........................................................................................ 17
4.2.1 Hardware Reset ..................................................................................................... 17
4.2.2 Software Reset....................................................................................................... 17
4.3 Analog to Digital Converter............................................................................................... 19
4.3.1 Pin Connection ....................................................................................................... 19
4.3.2 ADC Characteristics ............................................................................................... 20
4.3.3 Sync. Signal Support.............................................................................................. 21
4.3.4 Clock Recovery ...................................................................................................... 22
4.3.5 Sampling Phase Adjustment .................................................................................. 23
4.4 Ultra-Reliable Digital Visual Receiver (DVI Rx)................................................................. 25
4.4.1 DVI Receiver Characteristics.................................................................................. 25
4.4.2 HDCP (High-Bandwidth Digital Content Protection System) .................................. 26
4.5 ITU-R BT656 Video Input ................................................................................................. 27
4.5.1 YCbCr Input Clamping ........................................................................................... 27
4.6 Image Capture Active Window Decoder ........................................................................ 28
4.6.1 ADC Capture Window ............................................................................................ 28
4.6.2 DVI Capture Window.............................................................................................. 30
4.6.3 ITU-R BT656 Capture Window............................................................................... 30
4.7 Image Measurement......................................................................................................... 32
4.7.1 Input Format Measurement (IFM)........................................................................... 32
4.7.2 Input Data Measurement........................................................................................ 34
4.8 Digital Color Controls........................................................................................................ 36
4.8.1 YUV Hue / Saturation Controls............................................................................... 36
4.8.2 RealColor Flesh tone Adjustment........................................................................... 37
4.8.3 RGB Black Level / Contrast / Brightness................................................................ 37
4.8.4 Input Look-up Table ............................................................................................... 38
4.9 Horizontal Shrink .............................................................................................................. 39
4.10 Frame Store Interface..................................................................................................... 40
4.10.1 Supported SDRAM Devices ................................................................................. 40
4.10.2 Adjustable Frame Store Interface Delays............................................................. 40
Genesis Microchip
gm5060/gm5060-H Data Sheet
February 2002
C5060-DAT-01G
v
4.10.3 Frame Store Bandwidth Requirements ................................................................ 40
4.10.4 SDRAM Power On Sequence .............................................................................. 41
4.10.5 SDRAM Power Down ........................................................................................... 41
4.10.6 Pan and Crop Operations..................................................................................... 41
4.10.7 Double Buffering Frame Store Bandwidth Requirements..................................... 42
4.10.8 Freeze Frame....................................................................................................... 42
4.10.9 Interlaced Formats and De-interlacing ................................................................. 42
4.11 Scaling............................................................................................................................ 43
4.11.1 Pixel Replication Scaling ...................................................................................... 43
4.11.2 Vertical Shrink ...................................................................................................... 43
4.11.3 Adaptive Contrast Enhancement (ACE) ............................................................... 43
4.12 Gamma Correction LUT.................................................................................................. 44
4.12.1 Gamma Correction ............................................................................................... 44
4.12.2 Moir Cancellation................................................................................................ 45
4.13 Display Timing and Control............................................................................................. 46
4.13.1 Display Clock Generation Display Digital Direct Synthesis Block (DDDS) ........ 46
4.13.2 Display Synchronization ....................................................................................... 47
4.13.3 Display Port Timing .............................................................................................. 49
4.14 Data Path Bypass Options.............................................................................................. 51
4.15 OSD................................................................................................................................ 53
4.15.1 Character Mapped OSD ....................................................................................... 53
4.15.2 Bitmapped OSD ................................................................................................... 59
4.15.3 Color Look-up Table (LUT)................................................................................... 59
4.15.4 Multiple OSD Windows......................................................................................... 59
4.15.5 OSD Stretch ......................................................................................................... 59
4.15.6 Blending ............................................................................................................... 59
4.15.7 OSD Merge .......................................................................................................... 60
4.16 On-Chip Microprocessor................................................................................................. 61
4.17 Bootstrap Configuration .................................................................................................. 62
4.18 Host Interface ................................................................................................................. 63
4.18.1 2-wire Configuration ............................................................................................. 63
4.18.2 6-Wire Configuration ............................................................................................ 66
4.19 Miscellaneous Functions ................................................................................................ 69
4.19.1 General Purpose Inputs and Outputs (GPIO's) .................................................... 69
4.19.2 Pulse Width Modulation (PWM) Back Light Control ............................................. 69
4.19.3 Low Power State .................................................................................................. 69
5. Electrical Specifications .......................................................................................................... 70
5.1 DC Characteristics............................................................................................................ 70
5.2 Preliminary AC Characteristics ......................................................................................... 72
6. Ordering Information ............................................................................................................... 76
7. Mechanical Specifications....................................................................................................... 77
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