HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: 4029B (Fairchild Semiconductor)

Presettable Binary/decade Up/down Counter

 

Скачать: PDF   ZIP
Fairchild Semiconductor
October 1987
Revised January 1999
CD402
9BC
Prese
tt
ab
le Binary/
D
e
cade
Up/
D
o
w
n Counter
1999 Fairchild Semiconductor Corporation
DS005960.prf
www.fairchildsemi.com
CD4029BC
Presettable Binary/Decade Up/Down Counter
General Description
The CD4029BC is a presettable up/down counter which
counts in either binary or decade mode depending on the
voltage level applied at binary/decade input. When binary/
decade is at logical "1", the counter counts in binary, other-
wise it counts in decade. Similarly, the counter counts up
when the up/down input is at logical "1" and vice versa.
A logical "1" preset enable signal allows information at the
"jam" inputs to preset the counter to any state asynchro-
nously with the clock. The counter is advanced one count
at the positive-going edge of the clock if the carry in and
preset enable inputs are at logical "0". Advancement is
inhibited when either or both of these two inputs is at logi-
cal "1". The carry out signal is normally at logical "1" state
and goes to logical "0" state when the counter reaches its
maximum count in the "up" mode or the minimum count in
the "down" mode provided the carry input is at logical "0"
state.
All inputs are protected against static discharge by diode
clamps to both V
DD
and V
SS
.
Features
s
Wide supply voltage range:
3V to 15V
s
High noise immunity:
0.45 V
DD
(typ.)
s
Low power TTL compatibility:
fan out of 2 driving 74L
or 1 driving 74LS
s
Parallel jam inputs
s
Binary or BCD decade up/down counting
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Top View
Order Number
Package Number
Package Description
CD4029BCWM
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide body
CD4029BCSJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4029BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
C
D
40
29BC
Logic Diagram
3
www.fairchildsemi.com
CD402
9BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 2)
Note 3: I
OH
and I
OL
are tested one output at a time.
DC Supply Voltage (V
DD
)
-
0.5V to
+
18 V
DC
Input Voltage (V
IN
)
-
0.5V to V
DD
+
0.5 V
DC
Storage Temperature Range (T
S
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
DC Supply Voltage (V
DD
)
3V to 15 V
DC
Input Voltage (V
IN
)
0V to V
DD
V
DC
Operating Temperature Range (T
A
)
-
40
C to
+
85
C
Symbol
Parameter
Conditions
-
40
C
+
25
C
+
85
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
=
5V
20
20
150
A
V
DD
=
10V
40
40
300
A
V
DD
=
15V
80
80
600
A
V
OL
LOW Level
|I
O
|
<
1
A
Output Voltage
V
DD
=
5V
0.05
0
0.05
0.05
V
V
DD
=
10V
0.05
0
0.05
0.05
V
V
DD
=
15V
0.05
0
0.05
0.05
V
V
OH
HIGH Level
|I
O
|
<
1
A
Output Voltage
V
DD
=
5V
4.95
4.95
5
4.95
V
V
DD
=
10V
9.95
9.95
10
9.95
V
V
DD
=
15V
14.95
14.95
15
14.95
V
V
IL
LOW Level
V
DD
=
5V, V
O
=
0.5V or 4.5V
1.5
1.5
1.5
V
Input Voltage
V
DD
=
10V, V
O
=
1V or 9V
3.0
3.0
3.0
V
V
DD
=
15V, V
O
=
1.5V or 13.5V
4.0
4.0
4.0
V
V
IH
HIGH Level
V
DD
=
5V, V
O
=
0.5V or 4.5V
3.5
3.5
3.5
V
Input Voltage
V
DD
=
10V, V
O
=
1V or 9V
7.0
7.0
7.0
V
V
DD
=
15V, V
O
=
1.5V or 13.5V
11.0
11.0
11.0
V
I
OL
LOW Level Output
V
DD
=
5V, V
O
=
0.4V
0.52
0.44
0.88
0.36
mA
Current (Note 3)
V
DD
=
10V, V
O
=
0.5V
1.3
1.1
2.25
0.9
mA
V
DD
=
15V, V
O
=
1.5V
3.6
3.0
8.8
2.4
mA
I
OH
HIGH Level Output
V
DD
=
5V, V
O
=
4.6V
-
0.52
-
0.44
-
0.88
-
0.36
mA
Current (Note 3)
V
DD
=
10V, V
O
=
9.5V
-
1.3
-
1.1
-
2.25
-
0.9
mA
V
DD
=
15V, V
O
=
13.5V
-
3.6
-
3.0
-
8.8
-
2.4
mA
I
IN
Input Current
V
DD
=
15V, V
IN
=
0V
-
0.3
-
10
-
5
-
0.3
-
1.0
A
V
DD
=
15V, V
IN
=
15V
0.3
10
-
5
0.3
1.0
A
www.fairchildsemi.com
4
C
D
40
29BC
AC Electrical Characteristics
(Note 4)
T
A
=
25
C, C
L
=
50 pF, R
L
=
200k, Input t
rCL
=
t
fCL
=
20 ns, unless otherwise specified
Note 4: *AC Parameters are guaranteed by DC correlated testing.
Note 5: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CLOCKED OPERATION
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
200
400
ns
to Q Outputs
V
DD
=
10V
85
170
ns
V
DD
=
15V
70
140
ns
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
320
640
ns
to Carry Output
V
DD
=
10V
135
270
ns
V
DD
=
15V
110
220
ns
t
PHL
or t
PLH
Propagation Delay Time
C
L
=
15 pF
to Carry Output
V
DD
=
5V
285
570
ns
V
DD
=
10V
120
240
ns
V
DD
=
15V
95
190
ns
t
THL
or t
TLH
Transition Time/Q
V
DD
=
5V
100
200
ns
or Carry Output
V
DD
=
10V
50
100
ns
V
DD
=
15V
40
80
ns
t
WH
or t
WL
Minimum Clock
V
DD
=
5V
160
320
ns
Pulse Width
V
DD
=
10V
70
135
ns
V
DD
=
15V
55
110
ns
t
rCL
or t
fCL
Maximum Clock Rise
V
DD
=
5V
15
s
and Fall Time
V
DD
=
10V
10
s
V
DD
=
15V
5
s
t
SU
Minimum Set-Up Time
V
DD
=
5V
180
360
ns
V
DD
=
10V
70
140
ns
V
DD
=
15V
55
110
ns
f
CL
Maximum Clock Frequency
V
DD
=
5V
1.5
3.1
MHz
V
DD
=
10V
3.7
7.4
MHz
V
DD
=
15V
4.5
9
MHz
C
IN
Average Input Capacitance
Any Input
5
7.5
pF
C
PD
Power Dissipation Capacitance
Per Package (Note 5)
65
pF
PRESET ENABLE OPERATION
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
285
570
ns
to Q output
V
DD
=
10V
115
230
ns
V
DD
=
15V
95
195
ns
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
400
800
ns
to Carry Output
V
DD
=
10V
165
330
ns
V
DD
=
15V
135
260
ns
t
WH
Minimum Preset Enable
V
DD
=
5V
80
160
ns
Pulse Width
V
DD
=
10V
30
60
ns
V
DD
=
15V
25
50
ns
t
REM
Minimum Preset Enable
V
DD
=
5V
150
300
ns
Removal Time
V
DD
=
10V
60
120
ns
V
DD
=
15V
50
100
ns
CARRY INPUT OPERATION
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
265
530
ns
to Carry Output
V
DD
=
10V
110
220
ns
V
DD
=
15V
90
180
ns
t
PHL
, t
PLH
Propagation Delay Time
C
L
=
15 pF
to Carry Output
V
DD
=
5V
200
400
ns
V
DD
=
10V
85
170
ns
V
DD
=
15V
70
140
ns
5
www.fairchildsemi.com
CD402
9BC
Logic Waveforms
Decade Mode
Binary Mode
© 2017 • ChipFind
Контакты
Главная страница