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Datasheet: 100329A (Fairchild Semiconductor)

Low Power Octal Ecl/ttl Bidirectional Translator With Register

 

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Fairchild Semiconductor
2000 Fairchild Semiconductor Corporation
DS500047
www.fairchildsemi.com
August 1989
Revised August 2000
1
00329A L
o
w

Power
O
c
tal
ECL/
TTL Bi
dir
ect
ional
T
r
ansl
ator
wi
th
Regist
er
100329A
Low Power Octal ECL/TTL Bidirectional Translator with
Register
General Description
The 100329A is an octal registered bidirectional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of the translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. The outputs change
synchronously with the rising edge of the clock input (CP)
even though only one output is enabled at the time.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is
-
2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces the termination power and prevents
loss of low state noise margin when several loads share
the bus.
The 100329A is designed with FAST
TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 k
pull-down resistors.
Features
s
Bidirectional translation
s
ECL high impedance outputs
s
Registered outputs
s
FAST TTL outputs
s
3-STATE outputs
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
s
High drive IOS
Ordering Code:
Logic Symbol
Pin Descriptions
All pins function at 100K ECL levels except for T
0
T
7
.
Connection Diagram
FAST
is a registered trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
100329APC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Pin Names
Description
E
0
E
7
ECL Data I/O
T
0
T
7
TTL Data I/O
OE
Output Enable Input
CP
Clock Pulse Input
(Active Rising Edge)
DIR
Direction Control Input
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2
10032
9A
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
Z
=
High Impedance
[N]
=
LOW-to-HIGH Clock Transition
NC
=
No Change
Functional Diagram
Note: DIR and OE use ECL logic levels
Detail
Note 1: ECL input to TTL output mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before CP.
OE
DIR
CP
ECL
TTL
Notes
Port
Port
L
L
X
Input
Z
1, 3
L
H
X
LOW
Input
2, 3
(Cut-Off)
H
L
[N]
L
L
1
H
L
[N]
H
H
1
H
L
L
X
NC
1, 3
H
H
[N]
L
L
2
H
H
[N]
H
H
2
H
H
L
NC
X
2, 3
3
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1
00329A
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
Note 4: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 5: ESD testing conforms to MIL-STD-883, Method 3015.
Note 6: Either voltage limit or current limit is sufficient to protect inputs.
TTL-to-ECL DC Electrical Characteristics
(Note 7)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C, V
TTL
=
+
4.5V to
+
5.5V
Note 7: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
j
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
V
TTL
Pin Potential to Ground Pin
-
0.5V to
+
6.0V
ECL Input Voltage (DC)
V
EE
to
+
0.5V
ECL Output Current
(DC Output HIGH)
-
50 mA
TTL Input Voltage (Note 6)
-
0.5V to
+
6.0V
TTL Input Current (Note 6)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to TTL Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD (Note 5)
2000V
Case Temperature (T
C
)
0
C to
+
85
C
ECL Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
TTL Supply Voltage (V
TTL
)
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH
(Max) or V
IL
(Min)
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
Loading with 50
to
-
2V
Cutoff Voltage
OE or DIR LOW,
-
2000
-
1950
mV
V
IN
=
V
IH
(Max) or V
IL
(Min)
Loading with 50
to
-
2V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH
(Min) or V
IL
(Max)
Corner Point HIGH
Loading with 50
to
-
2V
V
OLC
Output LOW Voltage
-
1610
mV
Corner Point LOW
V
IH
Input HIGH Voltage
2.0
5.0
V
Over V
TTL
, V
EE
, T
C
Range
V
IL
Input LOW Voltage
0
0.8
V
Over V
TTL
, V
EE
, T
C
Range
I
IH
Input HIGH Current
70
A
V
IN
=
+
2.7V
Breakdown Test
1.0
mA
V
IN
=
+
5.5V
I
IL
Input LOW Current
-
700
A
V
IN
=
+
0.5V
V
FCD
Input Clamp
-
1.2
V
I
IN
=
-
18 mA
Diode Voltage
I
EE
V
EE
Supply Current
LE LOW, OE and DIR HIGH
Inputs OPEN
-
189
-
94
mA
V
EE
=
-
4.2V to
-
4.8V
-
199
-
94
V
EE
=
-
4.2V to
-
5.7V
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4
10032
9A
ECL-to-TTL DC Electrical Characteristics
(Note 8)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C, C
L
=
50 pF, V
TTL
=
+
4.5V to
+
5.5V
Note 8: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
DIP TTL-to-ECL AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
TTL
=
+
4.5V to
+
5.5V, V
CC
=
V
CCA
=
GND
DIP ECL-to-TTL AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
TTL
=
+
4.5V to
+
5.5V, V
CC
=
V
CCA
=
GND, C
L
=
50.pF
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
2.7
3.1
V
I
OH
=
-
3 mA, V
TTL
=
4.75V
2.4
2.9
V
I
OH
=
-
3 mA, V
TTL
=
4.50V
V
OL
Output LOW Voltage
0.3
0.5
V
I
OL
=
24 mA, V
TTL
=
4.50V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
I
IH
Input HIGH Current
350
A
V
IN
=
V
IH
(Max)
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL
(Min)
I
OZHT
3-STATE Current Output HIGH
70
A
V
OUT
=
+
2.7V
I
OZLT
3-STATE Current Output LOW
-
700
A
V
OUT
=
+
0.5V
I
OS
Output Short-Circuit Current
-
225
-
100
mA
V
OUT
=
0.0V, V
TTL
=
+
5.5V
I
TTL
V
TTL
Supply Current
74
mA
TTL Outputs LOW
49
mA
TTL Outputs HIGH
67
mA
TTL Outputs in 3-STATE
Symbol
Parameter
T
C
=
0
C
T
C
=
25
C
T
C
=
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
f
MAX
Max Toggle Frequency
350
350
350
MHz
t
PLH
CP to E
n
1.7
3.6
1.7
3.7
1.9
3.9
ns
Figures 1, 2
t
PHL
t
PZH
OE to E
n
1.3
4.2
1.5
4.4
1.7
4.8
ns
Figures 1, 2
(Cut-off to HIGH)
t
PHZ
OE to E
n
1.5
4.5
1.6
4.5
1.6
4.6
ns
Figures 1, 2
(HIGH to Cut-off)
t
PHZ
DIR to E
n
1.6
4.3
1.6
4.3
1.7
4.5
ns
Figures 1, 2
(HIGH to Cut-off)
t
set
T
n
to CP
1.1
1.1
1.1
ns
Figures 1, 2
t
hold
T
n
to CP
1.7
1.7
1.9
ns
Figures 1, 2
t
pw
(H)
Pulse Width CP
2.1
2.1
2.1
ns
Figures 1, 2
t
TLH
Transition Time
0.6
1.6
0.6
1.6
0.6
1.6
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
Symbol
Parameter
T
C
=
0
C
T
C
=
25
C
T
C
=
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
f
MAX
Max Toggle Frequency
125
125
125
MHz
t
PLH
CP to T
n
3.1
7.2
3.1
7.2
3.3
7.7
ns
Figures 3, 4
t
PHL
t
PZH
OE to T
n
3.4
8.45
3.7
8.95
4.0
9.7
ns
Figures 3, 5
t
PZL
(Enable Time)
3.8
9.2
4.0
9.2
4.3
9.95
t
PHZ
OE to T
n
3.2
8.95
3.3
8.95
3.5
9.2
ns
Figures 3, 5
t
PLZ
(Disable Time)
3.0
7.7
3.4
8.7
4.1
9.95
t
PHZ
DIR to T
n
2.7
8.2
2.8
8.7
3.1
8.95
ns
Figures 3, 6
t
PLZ
(Disable Time)
2.8
7.45
3.1
7.95
4.0
9.2
t
set
E
n
to CP
1.1
1.1
1.1
ns
Figures 3, 4
t
hold
E
n
to CP
2.1
2.1
2.6
ns
Figures 3, 4
t
pw
(H)
Pulse Width CP
4.1
4.1
4.1
ns
Figures 3, 4
5
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1
00329A
Test Circuitry
(TTL-to-ECL)
Note: R
T
=
50
termination resistive load. When an input or output is being monitored by a scope, R
T
is supplied by the scope's 50
input resistance. When
an input or output is not being monitored, an external 50
resistance must be applied to serve as R
T
.
Note: TTL and ECL force signals are brought to the DUT via 50
coax lines.
Note: V
TTL
is decoupled to ground with 0.1
F, V
EE
is decoupled to ground with 0.01
F and V
CC
is connected to ground.
FIGURE 1. TTL-to-ECL AC Test Circuit
Switching Waveforms
(TTL-to-ECL)
FIGURE 2. TTL to ECL Transition--Propagation Delay and Transition Times
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