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Datasheet: 100322QC (Fairchild Semiconductor)

Low Power 9-Bit Buffer

 

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Fairchild Semiconductor
2000 Fairchild Semiconductor Corporation
DS010608
www.fairchildsemi.com
October 1989
Revised August 2000
1
00322 Low
Power 9-Bi
t Buff
er
100322
Low Power 9-Bit Buffer
General Description
The 100322 is a monolithic 9-bit buffer. The device con-
tains nine non-inverting buffer gates with single input and
output. All inputs have 50 k
pull-down resistors and all
outputs are buffered.
Features
s
30% power reduction of the 100122
s
2000V ESD protection
s
Pin/function compatible with 100122
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
s
Available to MIL-STD-883
s
Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number
Package Number
Package Description
100322PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100322QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100322QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
Pin Names
Description
D
1
, D
9
Data Inputs
O
1
, O
9
Data Outputs
Inputs
Outputs
D
1
- D
9
O
1
- O
9
L
L
H
H
www.fairchildsemi.com
2
100322
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 3)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
DIP AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 4: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with multiple outputs switching.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
50 mA
ESD (Note 2)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH (Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
or V
IL (Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH(Min)
Loading with
V
OLC
Output LOW Voltage
-
1610
or V
IL (Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal
for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal
for All Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL (Min)
I
IH
Input HIGH Current
240
A
V
IN
=
V
IH (Max)
I
EE
Power Supply Current
-
65
-
30
mA
Inputs Open
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.45
1.45
0.45
1.45
0.45
1.55
ns
Figures 1, 2
t
PHL
Data to Output
(Note 4)
t
TLH
Transition Time
0.35
1.20
0.35
1.20
0.35
1.20
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
3
www.fairchildsemi.com
1
00322
Commercial Version
(Continued)
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with multiple outputs switching.
Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (t
OSHL
), or LOW to HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
PS
guaranteed by design.
Industrial Version
PLCC DC Electrical Characteristics
(Note 7)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
-
40
C to
+
85
C
Note 7: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 8: The propagation delay specified is for single output switching. Delays may vary up to 200 ps with multiple outputs switching.
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.45
1.25
0.45
1.25
0.45
1.35
ns
Figures 1, 2
t
PHL
Data to Output
(Note 5)
t
TLH
Transition Time
0.35
1.10
0.35
1.10
0.35
1.10
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
t
OSHL
Maximum Skew Common Edge
Output-to-Output Variation
200
200
200
ps
(Note 6)
Data to Output Path
t
OSLH
Maximum Skew Common Edge
Output-to-Output Variation
200
200
200
ps
(Note 6)
Data to Output Path
t
OST
Maximum Skew Opposite Edge
Output-to-Output Variation
260
260
260
ps
(Note 6)
Data to Output Path
t
PS
Maximum Skew
Pin (Signal) Transition Variation
200
200
200
ps
(Note 6)
Data to Output Path
Symbol
Parameter
T
C
=
-
40
C
T
C
=
0
C to
+
85
C
Units
Conditions
Min
Max
Min
Max
V
OH
Output HIGH Voltage
-
1085
-
870
-
1025
-
870
mV
V
IN
=
V
IH (Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1575
-
1830
-
1620
or V
IL (Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1095
-
1035
mV
V
IN
=
V
IH (Min)
Loading with
V
OLC
Output LOW Voltage
-
1565
-
1610
or V
IL (Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1170
-
870
-
1165
-
870
mV
Guaranteed HIGH Signal
for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1480
-
1830
-
1475
mV
Guaranteed LOW Signal
for All Inputs
I
IL
Input LOW Current
0.50
0.50
A
V
IN
=
V
IL (Min)
I
IH
Input HIGH Current
300
240
A
V
IN
=
V
IH (Max)
I
EE
Power Supply Current
-
65
-
30
-
65
-
30
mA
Inputs Open
Symbol
Parameter
T
C
=
-
40
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.45
1.25
0.45
1.25
0.45
1.35
ns
Figures 1, 2
t
PHL
Data to Output
(Note 8)
t
TLH
Transition Time
0.30
1.20
0.35
1.10
0.35
1.10
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
www.fairchildsemi.com
4
100322
Test Circuit
Notes:
V
CC
, V
CCA
=
+
2V, V
EE
=
-
2.5V
L1 and L2
=
equal length 50
impedance lines
R
T
=
50
terminator internal to scope
Decoupling 0.1
F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
=
Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay and Transition Times
5
www.fairchildsemi.com
1
00322
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
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