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Datasheet: 100311QI (Fairchild Semiconductor)

Low Skew 1:9 Differential Clock Driver

 

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Fairchild Semiconductor
1999 Fairchild Semiconductor Corporation
DS010648
www.fairchildsemi.com
February 1990
Revised November 1999
1
0031
1 Low
Skew
1
:
9 Dif
f
er
enti
al

Clo
ck
Dr
iver
100311
Low Skew 1:9 Differential Clock Driver
General Description
The 100311 contains nine low skew differential drivers,
designed for generation of multiple, minimum skew differ-
ential clocks from a single differential input (CLKIN,
CLKIN). If a single-ended input is desired, the V
BB
output
pin may be used to drive the remaining input line. A HIGH
on the enable pin (EN) will force a LOW on all of the CLK
n
outputs and a HIGH on all of the CLK
n
output pins. The
100311 is ideal for distributing a signal throughout a system
without worrying about the original signal becoming too
corrupted by undesirable delays and skew.
Features
s
Low output-to-output skew
s
2000V ESD protection
s
1:9 low skew clock driver
s
Differential inputs and outputs
s
Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
28-Pin PLCC
Truth Table
Order Number
Package Number
Package Description
100311QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100311QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
Pin Names
Description
CLKIN, CLKIN
Differential Clock Inputs
EN
Enable
CLK
08
, CLK
08
Differential Clock Outputs
V
BB
V
BB
Output
NC
No Connect
CLKIN
CLKIN
EN
CLK
n
CLK
n
L
H
L
L
H
H
L
L
H
L
X
X
H
L
H
www.fairchildsemi.com
2
10031
1
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 3)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
Pin Potential to Ground Pin (V
EE
)
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
50 mA
ESD (Note 2)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
or V
IL
(Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH
Loading
with
V
OLC
Output LOW Voltage
-
1610
mV
or V
IL
(Max)
50
to
-
2.0V
V
BB
Output Reference Voltage
-
1380
-
1320
-
1260
mV
I
VBB
=
-
300
A
V
DIFF
Input Voltage Differential
150
mV
Required for Full Output Swing
V
CM
Common Mode Voltage
V
CC
-
2.0
V
CC
-
0.5
V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for
All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for
All Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current
V
IN
=
V
IH
(Max)
CLKIN, CLKIN
100
A
EN
250
I
CBO
Input Leakage Current
-
10
A
V
IN
=
V
EE
I
EE
Power Supply Current
-
115
-
57
mA
Inputs Open
3
www.fairchildsemi.com
1
0031
1
Commercial Version
(Continued)
AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 4: f
MAX
=
the highest frequency at which output V
OL
/V
OH
levels still meet V
IN
specifications. The F311 will function @ 1 GHz.
Note 5: t
PS
describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW prop-
agation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin.
Note 6: t
OSLH
describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; t
OSHL
describes the same con-
ditions except with the outputs going HIGH-to-LOW.
Note 7: t
OST
describes the maximum worst case difference in any of the t
PS
, t
OSLH
or t
OST
delay paths combined.
Note 8: The skew specifications pertain to differential I/O paths.
Industrial Version
DC Electrical Characteristics
(Note 9)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
-
40
C to
+
85
C
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
MAX
Max Toggle Frequency
750
750
750
MHz
(Note 4)
CLKIN to Q
n
t
PLH
Propagation Delay,
t
PHL
CLKIN
n
to CLK
n
Differential
0.75
0.84
0.95
0.75
0.86
0.95
0.84
0.93
1.04
ns
Figure 3
Single-Ended
0.65
0.90
1.05
0.67
0.93
1.17
0.74
1.06
1.24
t
PLH
Propagation Delay
0.75
1.03
1.20
0.80
1.05
1.25
0.85
1.12
1.35
ns
Figure 2
t
PHL
SEL to Output
t
PS
LHHL Skew
10
30
10
30
10
30
ps
(Note 5)(Note 8)
t
OSLH
GateGate Skew LH
20
50
20
50
20
50
(Note 6)(Note 8)
t
OSHL
GateGate Skew HL
20
50
20
50
20
50
(Note 6)(Note 8)
t
OST
GateGate LHHL Skew
30
60
30
60
30
60
(Note 7)(Note 8)
t
S
Setup Time
250
250
300
ps
EN
n
to CLKIN
n
t
H
Hold Time
0
0
0
ps
EN
n
to CLKIN
n
t
R
Release Time
300
300
300
ps
EN
n
to CLKIN
n
t
TLH
Transition Time
275
500
750
275
480
750
275
460
750
ps
Figure 4
t
THL
20% to 80%, 80% to 20%
Symbol
Parameter
T
C
=
-
40
C
T
C
=
0
C to
+
85
C
Units
Conditions
Min
Max
Min
Max
V
OH
Output HIGH Voltage
-
1085
-
870
-
1025
-
870
mV
V
IN
=
V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1575
-
1830
-
1620
mV or
V
IL
(Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1095
-
1035
mV
V
IN
=
V
IH
Loading with
V
OLC
Output LOW Voltage
-
1565
-
1610
mV or
V
IL
(Min)
50
to
-
2.0V
V
BB
Output Reference Voltage
-
1395
-
1255
-
1380
-
1260
mV
I
VBB
=
-
300
A
V
DIFF
Input Voltage Differential
150
150
mV
Required for Full Output Swing
V
CM
Common Mode Voltage
V
CC
-
2.0 V
CC
-
0.5 V
CC
-
2.0 V
CC
-
0.5
V
V
IH
Input HIGH Voltage
-
1170
-
870
-
1165
-
870
mV
Guaranteed HIGH Signal for
All Inputs
www.fairchildsemi.com
4
10031
1
Industrial Version
(Continued)
DC Electrical Characteristics
(Note 9)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 9: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Note 10: f
MAX
=
the highest frequency of which output V
OL
/V
OH
levels still meet V
IN
specifications. The F311 will function @ 1 GHz
Note 11: t
PS
describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW prop-
agation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin.
Note 12: t
OSLH
describes in-phase gate differential propagation skews with all differential outputs going LOW-to-HIGH; t
OSHL
describes the same conditions
except with the outputs going HIGH-to-LOW.
Note 13: t
OST
describes the maximum worst case difference in any of the t
PS
, t
OSLH
or t
OST
delay paths combined.
Note 14: The skew specifications pertain to differential I/O paths.
Symbol
Parameter
T
C
=
-
40
C
T
C
=
0
C to
+
85
C
Units
Conditions
Min
Max
Min
Max
V
IL
Input LOW Voltage
-
1830
-
1480
-
1830
-
1475
mV
Guaranteed LOW Signal for
All Inputs
I
IL
Input LOW Current
0.50
0.50
A
V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current
V
IN
=
V
IH
(Max)
CLKIN, CLKIN
100
100
A
EN
250
250
I
CBO
Input Leakage Current
-
10
-
10
A
V
IN
=
V
EE
I
EE
Power Supply Current
-
115
-
57
-
115
-
57
mA Inputs
Open
V
PP
Minimum Input Swing
150
150
mV
V
CMR
Common Mode Range
V
CC
-
2.0
V
CC
-
0.5
V
CC
-
2.0
V
CC
-
0.5
V
Symbol
Parameter
T
C
=
-
40
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
MAX
Max Toggle Frequency
750
750
750
MHz
(Note 10)
CLKIN to Q
n
t
PLH
Propagation Delay,
t
PHL
CLKIN
n
to CLK
n
Differential
0.72
0.81
0.92
0.77
0.86
0.95
0.84
0.93
1.04
ns
Figure 3
Single-Ended
0.62
0.89
1.02
0.67
0.93
1.17
0.74
1.06
1.24
t
PLH
Propagation Delay
0.70
0.97
1.20
0.80
1.05
1.25
0.85
1.12
1.35
ns
Figure 2
t
PHL
SEL to Output
t
PS
LHHL Skew
10
30
10
30
10
30
(Note 11)(Note 14)
t
OSLH
GateGate Skew LH
20
50
20
50
20
50
ps
(Note 12)(Note 14)
t
OSHL
GateGate Skew HL
20
50
20
50
20
50
(Note 12)(Note 14)
t
OST
GateGate LHHL Skew
30
60
30
60
30
60
(Note 13)(Note 14)
t
S
Setup Time
250
250
300
ps
EN
n
to CLKIN
n
t
H
Hold Time
0
0
0
ps
EN
n
to CLKIN
n
t
R
Release Time
300
300
300
ps
EN
n
to CLKIN
n
t
TLH
Transition Time
275
500
750
275
480
750
275
460
750
ps
Figure 4
t
THL
20% to 80%, 80% to 20%
5
www.fairchildsemi.com
1
0031
1
Test Circuit
Note:
Shown for testing CLKIN to CLK1 in the differential mode.
L1, L2, L3 and L4
=
equal length 50
impedance lines.
All unused inputs and outputs are loaded with 50
in parallel with
3 pF to GND.
Scope should have 50
input terminator internally.
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay, EN to Outputs
FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs
FIGURE 4. Transition Times
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