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Datasheet: 100201SC (Fairchild Semiconductor)

Low Power 2-Input OR/NOR Gate/Inverter

 

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Fairchild Semiconductor
1999 Fairchild Semiconductor Corporation
DS011000
www.fairchildsemi.com
June 1992
Revised November 1999
1
00201 Low
Power 2-I
nput

OR/NOR
Gat
e
/I
nver
ter
100201
Low Power 2-Input OR/NOR Gate/Inverter
General Description
The 100201 is a 2-input OR/NOR Gate and a single
Inverter Gate in an eight pin SOIC package. All inputs have
50 k
pull-down resistors and all outputs are buffered. The
100201 is ideal for single gate needs or for use as the feed-
back loop of a crystal oscillator circuit.
Features
s
Small 8 lead 150 mil SOIC package
s
2000V ESD protection
s
300 MHz minimum F toggle
s
Temperature compensated
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
V
EE
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
100201SC
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.50" Narrow
Pin Names
Description
D
a
, D
1b
, D
2b
Data Inputs
O
b
Data Outputs
O
a
, O
b
Complementary Data Outputs
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2
100201
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 3)
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
GND, T
C
=
0
C to
+
85
C
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
SOIC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
GND
Note 4: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
50 mA
ESD (Note 2)
2000V
Operating Temperature (T
C
)
0
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH(Max)
or V
IL(Min)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH(Min)
or V
IL(Max)
Loading with
V
OLC
Output LOW Voltage
-
1610
mV
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL(Min)
I
IH
Input HIGH Current
240
A
V
IN
=
V
IH(Max)
I
EE
Power Supply Current
-
29
-
17
-
15
mA
Inputs OPEN
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.4
1.10
0.4
1.15
0.4
1.20
ns
Figure 1Figure 2
t
PHL
Data to Output
(Note 4)
t
TLH
Transition Time
0.40
1.20
0.40
1.20
0.40
1.20
ns
Figure 1Figure 2
t
THL
20% to 80%, 80% to 20%
3
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1
00201
Test Circuitry
Notes:
V
CC
, V
CCA
=
+
2V, V
EE
=
-
2.5V
L1 and L2
=
equal length 50
impedance lines
R
T
=
50
terminator internal to scope
Decoupling 0.1
F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
=
Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay and Transition Times
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4
10
0201 L
o
w

Power
2-I
nput
OR/NOR Gat
e
/I
nver
ter
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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