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Datasheet: U62256AS2A10LLG1 (No company)

STANDARD 32K X 8 SRAM

 

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U62256A
April 20, 2004
1
1
!
32768x8 bit static CMOS RAM
!
Access times 70 ns, 100 ns
!
Common data inputs and
data outputs
!
Three-state outputs
!
Typ. operating supply current
70 ns: 50 mA
100 ns: 40 mA
!
TTL/CMOS-compatible
!
Automatical reduction of power
dissipation in long Read Cycles
!
Power supply voltage 5 V + 10 %
!
Operating temperature ranges
0 to 70 C
-40 to 85
C
-40 to 125 C
!
QS 9000 Quality Standard
!
ESD protection > 2000 V
(MIL STD 883C M3015.7)
!
Latch-up immunity >100 mA
!
Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Standard 32K x 8 SRAM
Features
The U62256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Description
Pin Configuration
1
A14
VCC
28
2
A12
W
27
4
A6
A8
25
5
A5
A9
24
3
A7
A13
26
6
A4
A11
23
7
A3
G
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
Top View
Signal Name
Signal Description
A0 - A14
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
Pin Description
PDIP
SOP
U62256A
April 20, 2004
2
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read L
H
L
Data
Outputs
Low-Z
Write
L
L
*
Data Inputs High-Z
Truth Table
Block Diagram
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
CC
V
SS
W
G
E
Ro
w
A
d
d
r
e
s
s
In
p
u
t
s
Co
l
u
m
n
A
d
d
r
e
s
s
In
p
u
t
s
Address
Change
Detector
Co
l
u
m
n
De
c
o
d
e
r
Ro
w De
c
o
d
e
r
Sense Amplifier/
Write Control Logic
Clock
Generator
C
o
m
m
o
n
D
a
ta
I/
O
Memory Cell
Array
512 Rows x
64 x 8 Columns
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
* H or L
U62256A
April 20, 2004
3
3
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured 200 mV from steady-state voltage.
a
Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability
b
Maximum voltage is 7 V
c
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Absolute Maximum Ratings
a
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7
V
Input Voltage
V
I
-0.5
V
CC
+ 0.5
b
V
Output Voltage
V
O
-0.5
V
CC
+ 0.5
b
V
Power Dissipation
P
D
-
1
W
Operating Temperature
C-Type
K-Type
A-Type
T
a
0
-40
-40
70
85
125
C
Storage Temperature
C/K-Type
A-Type
T
stg
-65
-65
125
150
C
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
c
| I
OS
|
200
mA
d
-2 V at Pulse Width 10 ns
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Input Low Voltage
d
V
IL
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
U62256A
April 20, 2004
4
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
I
CC(OP)
I
CC(SB)
I
CC(SB)1
V
CC
V
IL
V
IH
t
cW
t
cW
V
CC
V
E
C-Type
K-Type
A-Type
V
CC
V
E
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
= 100 ns
= 5.5 V
= V
CC
- 0.2 V
= 5.5 V
= 2.2 V
70
65
5
10
50
1
mA
mA
A
A
A
mA
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
V
CC
I
OL
= 4.5 V
= -1.0 mA
= 4.5 V
= 3.2 mA
2.4
0.4
V
V
Input High Leakage Current
Input Low Leakage Current
I
IH
I
IL
V
CC
V
IH
V
CC
V
IL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
-2
2
A
A
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
CC
V
OL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
3,2
-1
mA
mA
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
I
OHZ
I
OLZ
V
CC
V
OH
V
CC
V
OL
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
-1
1
A
A
U62256A
April 20, 2004
5
5
Switching Characteristics
Read Cycle
Symbol
07
10
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
t
cR
70
100
ns
Address Access Time to Data Valid
t
AA
t
a(A)
70
100
ns
Chip Enable Access Time to Data Valid
t
ACE
t
a(E)
70
100
ns
Output Enable Access Time to Data Valid
t
OE
t
a(G)
35
45
ns
E HIGH to Output in High-Z
t
HZCE
t
dis(E)
25
35
ns
G HIGH to Output in High-Z
t
HZOE
t
dis(G)
25
35
ns
E LOW to Output in Low-Z
t
LZCE
t
en(E)
5
5
ns
G LOW to Output in Low-Z
t
LZOE
t
en(G)
0
0
ns
Output Hold Time from Address Change
t
OH
t
v(A)
5
5
ns
Switching Characteristics
Write Cycle
Symbol
07
10
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Write Cycle Time
t
WC
t
cW
70
100
ns
Write Pulse Width
t
WP
t
w(W)
55
70
ns
Write Pulse Width Setup Time
t
WP
t
su(W)
55
70
ns
Address Setup Time
t
AS
t
su(A)
0
0
ns
Address Valid to End of Write
t
AW
t
su(A-WH)
65
80
ns
Chip Enable Setup Time
t
CW
t
su(E)
65
80
ns
Pulse Width Chip Enable to End of Write
t
CW
t
w(E)
65
80
ns
Data Setup Time
t
DS
t
su(D)
30
35
ns
Data Hold Time
t
DH
t
h(D)
0
0
ns
Address Hold from End of Write
t
AH
t
h(A)
0
0
ns
W LOW to Output in High-Z
t
HZWE
t
dis(W)
25
35
ns
G HIGH to Output in High-Z
t
HZOE
t
dis(G)
25
35
ns
W HIGH to Output in Low-Z
t
LZWE
t
en(W)
0
0
ns
G LOW to Output in Low-Z
t
LZOE
t
en(G)
0
0
ns
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