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Datasheet: I90816 (No company)

Scalable Adsl Modem Digital Chip

 

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1
I90816
Product Data Sheet
Version 1.2 (March 1999)
Integrated Telecom Express, Inc.
I90816-Scalable ADSL Modem Digital Chip
Features
!
ADSL ATU-R digital chip
!
ANSI T1.413 issue 2, ITU-T G.992.1
(G.dmt), and G.992.2 (G.lite) compliant
!
Discrete multitone (DMT) modulation
!
Performance scalable, based on host
processor
!
Scalable data rate (up to 1.5 Mbps
downstream and 512 kbps upstream)
!
Reaches up to 18,000 feet in distance
!
Rate adaptive at 32 KB/s, depending on the
line condition
!
Supports Windows
98 and 2000 (NT 5.0)
!
Low power consumption
!
Software upgradable
!
Integrated 32-bit 33MHz PCI bus master
interface
!
Supports PCI power management
specification 2.2 D0 and D3 hot
!
PPP over ATM and Classical IP protocol
stack support for Windows 98/2000 (NT
5.0)
!
Supports third party host-based V.90
solution via standard AC97-link
!
Software selectable ADSL/V.90 operation
General Description
ITeX's I90816 is part of the ITeX Scalable ADSL
Modem (SAM) Chipset. The I90816 is intended
to be used with the I80134 SAM Analog Front
End (AFE). The I90816 is designed according
to the SAM concept, which scales the bit-rate
performance according to the available
computing resources. Some dedicated
hardware blocks are used for computation
intensive tasks, which provide maximum
programming flexibility. The rest of modulation
functions and system routines are performed by
the host system.
Block Diagram
PCI
Core
Control Reg
and Glue
Logic
Mem
F1
G1
State Machine
DC97
Execution Core
DSP
Front
End
2
I90816
Product Data Sheet
Version 1.2 (March 1999)
Integrated Telecom Express, Inc.
Introduction
The SAM Digital Chip consists of a bus
master PCI core, an execution core that
performs V.90 or ADSL DMT processing, an
ADSL DSP front end interface, and an AC97
interface.
Bus Master PCI Core
The bus master PCI core is responsible for
the transfer between the host processor
and the SAM Digital Execution Core. It has
the 33 MHz and 32-bit bus interface that
complies with the PCI 2.1 requirements.
Execution Core
The execution core performs partial ADSL
modulation functions. It consists of FFT,
IFFT, digital filters, and control register for
various systems needs. It is highly
programmable, allowing for future G.lite
standard revisions.
DSP Front End Interface
The I90816 includes a DSP front end
interface that communicates to the SAM
analog front end (I80134). It unloads some
of the digital signal processing functions
from the I80134 and also has a serial
interface for controlling I80134.
Pin Diagram
120
118
119
117
115
116
114
112
113
111
109
110
108
106
107
105
103
104
102
101
100
98
99
97
95
96
94
92
93
91
89
90
88
86
87
85
83
84
82
81
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
3
2
4
6
5
7
9
8
10
12
11
13
15
14
16
18
17
19
20
21
23
22
24
26
25
27
29
28
30
32
31
33
35
34
36
38
37
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
3
AD21
AD18
AD19
AD20
AD22
AD23
GND_IO
AD17
C/BE2#
AD16
GND_IO
GND_CORE
DEVSEL#
VDD_CORE
TRDY#
IRDY#
FRAME#
PAR
C/BE1#
SERR#
PERR#
STOP#
VDD_IO
AD13
AD14
AD15
AD9
GND_IO
AD10
AD11
AD12
GND_IO
EPROM_SEL
VDD_IO
DEBUG_0
VDD_IO
EPROM_DI
EPROM_DO
EPROM_CLK
L1LOOP
GND_IO
TxRxON
SCAN_TEST
L1DATA
L1HS
PWFAIL
SCAN_MODE
ExtRxGain0
ExtTxGain1
GND_IO
AD26
AD25
AD24
C/BE3#
IDSEL
GND_IO
AD27
PME
AD31
AD30
AD29
GNT#
REQ#
GND_IO
VDD_CORE
RST_
GND_CORE
PCI_CLK
INTA
OFFH
VOICE
CID
DSL_V90_
LCS
VDD_IO
SDATA_OUT
BIT_CLK
SDATA_IN
GND_IO
5V_REF
SYNC
GPI_1
VDD_IO
GPI_0
GPOUT
AD5
AD6
AD7
C/BE0#
AD8
AD4
GND_IO
AD0
AD1
AD2
AD3
VDD_IO
RESET_OUT_
RXD_0
GND_CORE
CTRL
PDOWN
RXD_1
NIBCLK
GND_IO
CLWD
GND_IO
MCLK
ECHO_2
ECHO_1
ECHO_0
VDD_IO
TXD_3
VDD_IO
I90816
SAM Digital Chip
VDD_CORE
GND_IO
TXD_0
TXD_1
TXD_2
GND_IO
GND_CORE
VDD_CORE
TEST_MOD1
EPROM_CS
ADSLRINGD
GND_IO
VDD_IO
GND_IO
RXD_3
RXD_2
ECHO_3
DEBUG_4
DEBUG_3
DEBUG_2
DEBUG_1
DEBUG_7
DEBUG_6
DEBUG_5
DEBUG_11
DEBUG_10
DEBUG_9
DEBUG_8
DEBUG_15
DEBUG_14
DEBUG_13
DEBUG_12
ExtTxGain1
ExtTxGain0
AD28
3
I90816
Product Data Sheet
Version 1.2 (March 1999)
Integrated Telecom Express, Inc.
Pin Assignment
Pin
No.
Pin Name
I/O
Pin No.
Pin Name
I/O
PCI
41
1
GND_IO
42
AD8
t/s
2
AD23
t/s
43
C/BE0_
t/s
3
AD22
t/s
44
AD7
t/s
4
AD21
t/s
45
AD6
t/s
5
AD20
t/s
46
AD5
t/s
6
AD19
t/s
47
AD4
t/s
7
AD18
t/s
48
GND_IO
8
GND_IO
49
VDD_IO
9
VDD_IO
50
AD3
t/s
10
AD17
t/s
51
AD2
t/s
11
AD16
t/s
52
AD1
t/s
12
C/BE2_
t/s
53
AD0
t/s
13
GND_IO
54
14
VDD_IO
I80134
15
FRAME_
s/t/s
55
RESET_OUT_
Out
16
IRDY_
s/t/s
56
PDOWN
Out
17
TRDY_
s/t/s
57
CTRL
Out
18
GND_CORE
58
GND_CORE
19
VDD_CORE
59
VDD_CORE
20
DEVSEL_
s/t/s
60
RXD_0
In
21
STOP_
s/t/s
61
RXD_1
In
22
PERR_
s/t/s
62
RXD_2
In
23
63
RXD_3
In
24
64
25
65
CLWD
In
26
SERR_
o/d
66
GND_IO
27
PAR
t/s
67
NIBCLK
In
28
C/BE1_
t/s
68
GND_IO
29
69
MCLK
In
30
70
GND_IO
31
GND_IO
71
VDD_IO
32
VDD_IO
72
ECHO_0
Out
33
AD15
t/s
73
ECHO_1
Out
34
AD14
t/s
74
ECHO_2
Out
35
AD13
t/s
75
ECHO_3
Out
36
AD12
t/s
76
37
AD11
t/s
77
TXD_0
Out
38
AD10
t/s
78
TXD_1
Out
39
AD9
t/s
79
TXD_2
Out
40
GND_IO
80
TXD_3
Out
4
I90816
Product Data Sheet
Version 1.2 (March 1999)
Integrated Telecom Express, Inc.
Pin
No.
Pin Name
I/O
Pin No.
Pin Name
I/O
81
EPROM_SEL
In
121
VDD_IO
82
GND_IO
AC-Link
83
VDD_IO
122
GPI_0
In
Debug and Test
123
GpOut
Out
84
DEBUG_0
Out
124
GPI_1
In
85
DEBUG_1
Out
125
5V_REF
86
DEBUG_2
Out
126
SYNC
Out
87
DEBUG_3
Out
127
SDATA_OUT
Out
88
DEBUG_4
Out
128
BIT_CLK
In
89
DEBUG_5
Out
129
SDATA_IN
In
90
DEBUG_6
Out
130
GND_IO
91
DEBUG_7
Out
131
VDD_IO
92
GND_IO
DAA
93
VDD_IO
132
ADSLRINGD
In
94
DEBUG_8
Out
133
LCS
In
95
DEBUG_9
Out
134
OFFH_
Out
96
DEBUG_10
Out
135
VOICE_
Out
97
DEBUG_11
Out
136
CID_
Out
98
DEBUG_12
Out
137
DSL_V90_
Out
99
DEBUG_13
Out
138
100
DEBUG_14
Out
101
DEBUG_15
Out
PCI
102
GND_CORE
139
INTA_
o/d*
103
VDD_CORE
140
104
TEST_MOD1 (g_oe_)
In
141
VDD_CORE
105
EPROM_CS
Out
142
RST_
In
106
EPROM_CLK
Out
143
GND_CORE
107
EPROM_DI
Out
144
PCI_CLK
In
108
EPROM_DO
In
145
GND_IO
109
SCAN_MODE
In
146
GNT_
In
PCB (spare)
147
REQ_
Out
110
ExtRxGain0
Out
148
PME_
o/d
111
ExtRxGain1
Out
149
AD31
t/s
112
ExtTxGain0
Out
150
AD30
t/s
113
ExtTxGain1
Out
151
AD29
t/s
114
SCAN_TEST
In
152
AD28
t/s
LEDs & General
Purpose
153
GND_IO
115
TxRxON_
Out
154
AD27
t/s
116
L1DATA_
Out
155
AD26
t/s
117
L1HS_
Out
156
AD25
t/s
118
PWFAIL_
In
157
AD24
t/s
119
L1LOOP_
Out
158
C/BE3_
t/s
120
GND_IO
159
IDSEL
In
160
GND_IO
5
I90816
Product Data Sheet
Version 1.2 (March 1999)
Integrated Telecom Express, Inc.
Pin Functional Description
Pin name
I/O
(buffer type)
Function
PCI
51
AD[31:0]
IO (t/s)
PCI Bus Address/Data. These signals represent a multiplexed PCI
address and data bus. A bus transaction consists of an address
phase followed by one or more data phases.
CBE[3:0]_
IO (t/s)
PCI Bus Command/Byte Enables. These signals act as a
multiplexed bus command or byte enables. During the address
phase of a transaction, CBE[3:0]_ defines the bus command.
During the subsequent data phase CBE[3:0]_ are used as byte
enables.
FRAME_
IO (s/t/s)
PCI Bus Cycle Frame. The signal FRAME_ is driven by the initiator
to indicate the beginning and duration of an access on the PCI bus.
I90816 samples the FRAME_ as a target and also drives the
FRAME_ as a bus master.
TRDY_
IO (s/t/s)
PCI Bus Target Ready. The target asserts this signal to indicate it
will complete the current data transfer phase. The I90816 chip
drives TRDY_ when acting as a target on the PCI bus and samples
TRDY_ when acting as an initiator on the PCI bus.
IRDY_
IO (s/t/s)
PCI Bus Initiator Ready. The signal is driven by the initiator to
indicate it will complete current data transfer phase. I90816 drives
IRDY_ when acting as an initiator and samples IRDY_ when acting
as a target. IRDY_ is active low.
STOP_
IO (s/t/s)
PCI Bus Stop Indicator. This signal is driven by the target to inform
the initiator
"
Target Abort
"
. This signal is driven by the target to
inform the initiator that the target attempts to stop current
transaction. The assertion of TRDY_ will determine the target
termination to be a
"
Target Disconnect
"
or a
"
Target Retry
"
.
I90816 drives STOP_ when acting as a target and samples STOP_
when acting as an initiator.
IDSEL
In
Initialization Device Select. This signal is used as a chip select
during configuration read/write transaction. When IDSEL is
asserted and the transaction is performed under type 0
configuration command, I90816 will respond as a target to the
transaction by asserting DEVSEL_.
DEVSEL_
IO (s/t/s)
PCI Interface Device Select. This signal indicates the driving device
has decoded its address as the target of the current access. As an
input, DEVSEL_ indicates whether a device on the bus has been
selected. I90816 samples the DEVSEL_ when acting as an initiator
on the bus. The transaction will be terminated with a
"
Master
Abort
"
except when the DEVSEL_ is sampled as asserted within
five cycles of FRAME_ assertion.
PAR
IO (t/s)
PCI Bus Parity Bit. Parity is even parity across AD[31:0] and
CBE[3:0]_. The PAR is stable and valid one clock after address
phase. As for data phase, the PAR is stable and valid one clock
after either IRDY_ is asserted in write transaction or TRDY_ is
asserted in read transaction. Once PAR is valid, it remains valid
until one clock after the completion of the current data phase.
When I90816 takes on the role of a master on the PCI bus, it will
drive PAR for address and write data phases. When I90816 acts as
a target on the PCI bus, it drives PAR for read data phase.
PERR_
IO (s/t/s)
PCI Bus Parity Error Detected. The PERR_ indicates a data parity
error during all PCI transactions except a special cycle. The PERR_
pin is sustained tri-state and must be driven active by the agent
receiving data two clocks following the data When a data parity
error is detected. Acting as a target, I90816 asserts PERR_ when it
detects a write data parity error. Acting as an initiator, I90816
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