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Datasheet: I90188 (No company)

Pci/utopia Interface Chip

 

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Integrated Telecom Express, Inc.
1
I90188
Product Data Sheets
Version 1.3 (July 1999)
I90188-PCI/Utopia Interface Chip
Features
!
PCI Interface
-
Compliant with PCI Specification
v2.2
-
32-bit address/data bus
-
Bus frequency up to 33 MHz
-
Supports PCI master/slave device
-
Supports +3.3V or +5V PCI interface
!
Utopia Interface
-
Utopia level 1 and 2 support for D0
and D3 hot
-
8-bit data path
-
Full duplex
-
Cell-based-only
!
Supports T1.413 issue 2, ITU-T G.992.1
(G.dmt), and G.992.2 (G.lite) full rate
speed
!
ITeX I90135 interface
!
AC'97 Digital Controller
-
Compliant with AC'97 Component
Specification R2.1
-
Provides standard AC97-link
interface for AC'97 modem codec
-
Supports multiple sample rates
!
Eight general purpose I/O pins
-
Can be individually enabled or
disabled via software configuration
registers
-
Can be individually set as input or
output via software configuration
registers
!
+3.3V & +5V Power Supply
!
Package: 160-pin PQFP
General Description
The I90188 is a PCI to the Utopia interface
and an AC97-link digital bridge device. The
I90188 has an 8-bit full duplex cell-based-
only Utopia interface that connects to an
ADSL controller. The AC'97 digital controller
provides an Intel AC'97 v2.1 standard AC-
link interface. The device's 32-bit PCI
interface supports PCI slave/master devices,
and is PCI specification v.2.2 compliant.
The I90188 requires a single 25 MHz clock
frequency input and supports a 3.3V power
supply. The I90188 is available in a 160-pin
PQFP.
Integrated Telecom Express, Inc.
2
I90188
Product Data Sheets
Version 1.3 (July 1999)
Block Diagram
RX FIFO 1 (16X32)
I90135
Control I/F
PCI
I/F
PCI
Configuration
Registers
DC'97
Utopia
I/F
Central
Configuration
Register
PCI Bus
TX FIFO (16X32)
TX FIFO (16X32)
TX FIFO (32X16)
RX FIFO (32X16)
I90188
Clock
Generator
25 MHz
Crystal
AC'97
Modem
Codec
RX FIFO 2 (16X32)
RX FIFO 3 (16X32)
RX FIFO 16 (16X32)
Integrated Telecom Express, Inc.
3
I90188
Product Data Sheets
Version 1.3 (July 1999)
Pin Diagram
I90188
PCI/Utopia I/F
160-pin PQFP
1
5
10
15
20
25
30
35
40
41
45
50
60
65
70
GND
IDSEL
AD12
AD9
105
95
90
85
81
115
120
75
121
125
135
130
140
145
150
155
160
AD4
V5
EPROM_SEL
PME#
EPROM_CLK
RXD4
GND
GND
RXADDR1
WR/RD#
RXD5
V5
SRESET#
RXD0
ARESET#
INT#
55
110
100
80
AD23
AD22 AD21
V3
AD20
AD19
AD18
AD17
GND
AD16
C/BE2#
FRAME#
IRDY#
V3
TRDY#
DEVSEL#
STOP#
GND
PERR#
SERR#
GND
PAR
C/BE1#
V3
AD15
AD13
GND
AD11
AD10
AD3
AD2
AD0
AD1
GND
TMODE0
GPIO0
PWRLOSS#
EPROM_DI
EPROM_CS
V3
EPROM_DO
V3
TXADDR0
TXADDR1
TXD0
TXD1
GND
TXD2
TXD4
TXD3
TXD5
TXCLAV
TXSOC
GND
TXENB#
TXD6
TXD7
V3
TXCLK
RXD6
RXD7
SAD5
SAD4
SAD0
SAD1
V3
AD14
V3
RXENB#
RXCLAV
RXSOC
RXCLK
RXADDR0
RXD3
READY#
CS#
ALE
SAD15
BE1
SAD14
SAD13
V3
SAD12
SAD11
SAD10
SAD9
SAD8
GND
SAD6
SAD3
SAD2
GND
SCANMODE
TXRXON
OHK
GND
DSL/V90#
RINGDET
LCDET
PILTONE
XOUT
GND
V5
XIN
V5
ACRESET#
SYNC
V35-AC97
SDATA_IN
V35-AC97
BIT_CLK
SDATA_OUT
GND
INTA
PCIRST#
PCICLK
GNT#
REQ#
V3
AD31
AD30
AD29
AD28
AD27
GND
AD26
AD25
AD24
C/BE3#
V3
SAD7
SCANTEST
AD8
V3
C/BE0#
AD7
AD6
AD5
RXD2
RXD1
Integrated Telecom Express, Inc.
4
I90188
Product Data Sheets
Version 1.3 (July 1999)
Pinout Table
Pin
Signal
1
GND
2
IDSEL
3
AD23
4
AD22
5
AD21
6
V3
7
AD20
8
AD19
9
AD18
10
AD17
11
GND
12
AD16
13
C/BE2#
14
FRAME#
15
IRDY#
16
V3
17
TRDY#
18
DEVSEL#
19
STOP#
20
GND
21
PERR#
22
SERR#
23
PAR
24
C/BE1#
25
V3
26
AD15
27
AD14
28
AD13
29
AD12
30
GND
31
AD11
32
AD10
33
AD9
34
AD8
35
V3
36
C/BE0#
37
AD7
38
AD6
39
AD5
40
GND
Pin
Signal
41
V3
42
AD4
43
AD3
44
AD2
45
AD1
46
GND
47
AD0
48
PME#
49
TMODE0
50
GPIO0
51
V5
52
PWRLOSS#
53
EPROM_DI
54
EPROM_CLK
55
EPROM_CS
56
EPROM_DO
57
V3
58
EPROM_SEL
59
TXADDR0
60
TXADDR1
61
TXD0
62
TXD1
63
GND
64
TXD2
65
TXD3
66
TXD4
67
TXD5
68
V3
69
TXD6
70
TXD7
71
TXENB#
72
TXCLAV
73
TXSOC
74
GND
75
TXCLK
76
RXENB#
77
RXCLAV
78
RXSOC
79
RXCLK
80
V3
Pin
Signal
81
GND
82
RXADDR1
83
RXADDR0
84
RXD7
85
RXD6
86
RXD5
87
V5
88
RXD4
89
RXD3
90
RXD2
91
RXD1
92
RXD0
93
SRESET#
94
GND
95
ARESET#
96
INT#
97
READY#
98
WR/RD#
99
CS#
100
ALE
101
BE1
102
SAD15
103
SAD14
104
SAD13
105
V3
106
SAD12
107
SAD11
108
SAD10
109
SAD9
110
SAD8
111
SAD7
112
GND
113
SAD6
114
SAD5
115
SAD4
116
SAD3
117
SAD2
118
SAD1
119
SAD0
120
GND
Pin
Signal
121
V3
122
SCANTEST
123
SCANMODE
124
TXRXON
125
OHK
126
GND
127
DSL/V90#
128
RINGDET
129
LCDET
130
PILTONE
131
GND
132
XOUT
133
V5
134
XIN
135
V5
136
ACRESET#
137
SYNC
138
V35-AC97
139
SDATA_IN
140
BIT_CLK
141
V35-AC97
142
SDATA_OUT
143
GND
144
INTA
145
PCIRST#
146
PCICLK
147
GNT#
148
REQ#
149
V3
150
AD31
151
AD30
152
AD29
153
AD28
154
AD27
155
GND
156
AD26
157
AD25
158
AD24
159
C/BE3#
160
V3
Integrated Telecom Express, Inc.
5
I90188
Product Data Sheets
Version 1.3 (July 1999)
Pin Description
Symbol
Pin #
Type
Description
POWER SUPPLIES
V3
6, 16, 25, 35, 41,
57, 68, 80, 105,
121, 149, 160
PWR
+3.3V OR +5V Power Supply for PCI bus, I90135 and
Utopia Interface.
V35-AC97
138, 141
PWR
+3.3V OR +5V Power Supply for AC'97 (AC-LINK) Interface
V5
51, 87, 133, 135
PWR
+5V Power Supply for PUB core.
GND
1, 11, 20, 30, 40,
46, 63, 74, 81, 94,
112, 120, 126,
131, 143, 155
GND
Ground.
PCI BUS INTERFACE SIGNALS
AD[31:0]
150 - 154, 156 -
158, 3 - 5, 7 - 10,
12, 26 - 29, 31 -
34, 37 - 39,
42 - 45, 47.
DI/O
PCI Multiplexed Address / Data 31 - 0.
32-bit bi-directional address/data multiplexed lines AD31 is the MSB
and AD0 is the LSB. The direction of these pins are defined below:
PHASE
Bus Master
Target
Address Phase
Output
Input
Read Data Phase
Input
Output
Write Data Phase
Output
Input
C/BE[3:0]#
159, 13, 24, 36
DI/O
Command/Byte Enable 3 - 0 #.
Multiplexed bus command and byte enables.
DEVSEL#
18
DI/O
Device Select #.
When driven active low, the signal indicates the driving device has
decoded its address as the target of the current access. This pin
acts as an output pin when the I90188 (including ISA slave) is the
slave of PCI bus cycle transaction. Otherwise, it is an input pin.
TRDY#
17
DI/O
Target Ready #.
This signal indicates that the target of the current data phase of the
transaction is ready to be completed. This pin acts as an output pin
when the I90188 (including ISA slave) is the slave of the PCI bus
cycle transaction. Otherwise, it is an input pin.
IRDY#
15
DI/O
Initiator Ready #.
This signal indicates that the initiator is ready to complete the
current data phase of the transaction. This pin acts as an output pin
when the I90188 is the bus master of the PCI bus. Otherwise, it is
an input pin.
FRAME#
14
DI/O
FRAME #.
This signal is driven by the initiator to indicate the beginning and
duration of a PCI access.
IDSEL
2
DI
Initialization Device Select.
This signal is used as a chip select during configuration read and
write transactions.
PAR
23
DI/O
Parity
This signal is used for the even parity check on both AD[31:0] &
C/BE[3:0]# lines. The PAR input/output direction follows the
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