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Datasheet: F49L400UA-70T (EliteMT (ESMT))

Org. = 256KbX16, Description = Flash 3.3V, Speed = 70/90 NS, Package = 48-TSOP

 

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EFST
preliminary
F49L400UA/F49L400BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.3 1/47
4 Mbit (512K x 8/256K x 16)
3V Only CMOS Flash Memory
1. FEATURES
!
Single supply voltage 3.0V-3.6V
!
Fast access time: 70/90 ns
!
524,288 x 8 / 262,144 x 16 switchable by BYTE pin
!
Compatible with JEDEC standard
- Pin-out, packages and software commands
compatible with single-power supply Flash
!
Low power consumption
- 7mA typical active current
- 25uA typical standby current
!
10,000 minimum program/erase cycles
!
Command register architecture
- Byte programming (9us typical)
- Sector Erase(sector structure: one 16 KB, two 8 KB,
one 32 KB, and seven 64 KB)
!
Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased
concurrently; Chip erase also provided.
- Automatically program and verify data at specified
address
!
Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
!
Ready/Busy (RY/ BY )
- RY/
BY
output pin for detection of program or erase
operation completion
!
End of program or erase detection
- Data polling
- Toggle bits
!
Hardware reset
- Hardware pin( ESET
R
) resets the internal state machine
to the read mode
!
Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors
from a program or erase operation.
!
Low V
CC
Write inhibit is equal to or less than 2.0V
!
Boot Sector Architecture
- U = Upper Boot Sector
- B = Bottom Boot Sector
!
Packages available:
- 48-pin TSOPI
2. ORDERING INFORMATION
Part No
Boot
Speed
Package
Part No
Boot
Speed
Package
F49L400UA-70T
Upper
70 ns
TSOPI
F49L400UA-90T
Upper
90 ns
TSOPI
F49L400BA-70T
Bottom
70 ns
TSOPI
F49L400BA-90T
Bottom
90 ns
TSOPI
3. GENERAL DESCRIPTION
The F49L400UA/F49L400BA is a 4 Megabit, 3V only
CMOS Flash memory device organized as 512K bytes of 8
bits or 256K words of 16bits. This device is packaged in
standard 48-pin TSOP. It is designed to be programmed
and erased both in system and can in standard EPROM
programmers.
With access times of 70 ns and 90 ns, the
F49L400UA/F49L400BA allows the operation of high-
speed microprocessors. The device has separate chip
enable CE, write enable WE , and output enable
OE
controls. EFST's memory devices reliably store memory
data even after 100,000 program and erase cycles.
The F49L400UA/F49L400BA is entirely pin and
command set compatible with the JEDEC standard for 4
Megabit Flash memory devices. Commands are written to
the command register using standard microprocessor write
timings.
The F49L400UA/F49L400BA features a sector erase
architecture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64
Kbytes. Sectors can be erased individually or in groups
without affecting the data in other sectors. Multiple-sector
erase and whole chip erase capabilities provide the
flexibility to revise the data in the device.
The sector protect/unprotect feature disables both
program and erase operations in any combination of the
sectors of the memory. This can be achieved in-system or
via programming equipment.
A low V
CC
detector inhibits write operations on loss of
power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the
Toggle Bit I feature on DQ6. Once the program or erase
cycle has been successfully completed, the device
internally resets to the Read mode.
EFST
preliminary
F49L400UA/F49L400BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.3 2/47
4. PIN CONFIGURATIONS
4.1 48-pin TSOP
4.2 Pin Description
Symbol
Pin Name
Functions
A0~A17
Address Input
To provide memory addresses.
DQ0~DQ14
Data Input/Output
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
DQ15/A-1
Q15 (Word mode) /
LSB addr (Byte Mode)
To bi-direction date I/O when BYTE is High
To input address when BYTE is Low
CE
Chip Enable
To activate the device when CE is low.
OE
Output Enable
To gate the data output buffers.
WE
Write Enable
To control the Write operations.
RESET
Reset
Hardware Reset Pin/Sector Protect Unprotect
BYTE
Word/Byte selection input
To select word mode or byte mode
RY/ BY
Ready/Busy
To check device operation status
V
CC
Power Supply
To provide power
GND
Ground
NC
No connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
F49L400U/BA
A15
A14
A13
A12
A11
A10
A9
A8
N C
N C
WE
RESET
N C
N C
RY/BY
N C
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
G ND
DQ15/A-1
DQ 7
DQ14
DQ 6
DQ13
DQ 5
DQ12
DQ 4
VCC
DQ11
DQ 3
DQ10
DQ 2
DQ 9
DQ 1
DQ 8
DQ 0
OE
G ND
CE
A0
EFST
preliminary
F49L400UA/F49L400BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.3 3/47
5. SECTOR STRUCTURE
Table 1: F49L400UA Sector Address Table
Sector Size
(Kbytes)
Address range
Sector Address
Sector
Byte
Mode
Word
Mode
Byte Mode
Word Mode
A18 A17 A16 A15 A14 A13
SA10
16
8K
7C000H-7FFFFH
3E000H-3FFFFH
1
1
1
1
1
X
SA9
8
4K
7A000H-7BFFFH
3D000H-3DFFFH
1
1
1
1
0
1
SA8
8
4K
78000H-79FFFH
3C000H-3CFFFH
1
1
1
1
0
0
SA7
32
16K
70000H-77FFFH
38000H-3BFFFH
1
1
1
0
X
X
SA6
64
32K
60000H-6FFFFH
30000H-37FFFH
1
1
0
X
X
X
SA5
64
32K
50000H-5FFFFH
28000H-2FFFFH
1
0
1
X
X
X
SA4
64
32K
40000H-4FFFFH
20000H-27FFFH
1
0
0
X
X
X
SA3
64
32K
30000H-3FFFFH
18000H-1FFFFH
0
1
1
X
X
X
SA2
64
32K
20000H-2FFFFH
10000H-17FFFH
0
1
0
X
X
X
SA1
64
32K
10000H-1FFFFH
08000H-0FFFFH
0
0
1
X
X
X
SA0
64
32K
00000H-0FFFFH
00000H-07FFFH
0
0
0
X
X
X
Note: Byte Mode: address range A17:A-1, Word mode : address range A17:A0
Table 2: F49L400BA Sector Address Table
Sector Size
(Kbytes)
Address range
Sector Address
Sector
Byte
Mode
Word
Mode
Byte Mode
Word Mode
A18 A17 A16 A15 A14 A13
SA10
64
32K
70000H-7FFFFH
38000H-3FFFFH
1
1
1
X
X
X
SA9
64
32K
60000H-6FFFFH
30000H-37FFFH
1
1
0
X
X
X
SA8
64
32K
50000H-5FFFFH
28000H-2FFFFH
1
0
1
X
X
X
SA7
64
32K
40000H-4FFFFH
20000H-27FFFH
1
0
0
X
X
X
SA6
64
32K
30000H-3FFFFH
18000H-1FFFFH
0
1
1
X
X
X
SA5
64
32K
20000H-2FFFFH
10000H-17FFFH
0
1
0
X
X
X
SA4
64
32K
10000H-1FFFFH
08000H-0FFFFH
0
0
1
X
X
X
SA3
32
16K
08000H-0FFFFH
04000H-07FFFH
0
0
0
1
X
X
SA2
8
4K
06000H-07FFFH
03000H-03FFFH
0
0
0
0
1
1
SA1
8
4K
04000H-05FFFH
02000H-02FFFH
0
0
0
0
1
0
SA0
16
8K
00000H-03FFFH
00000H-01FFFH
0
0
0
0
0
X
Note: Byte Mode: address range A17:A-1, Word mode : address range A17:A0
EFST
preliminary
F49L400UA/F49L400BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.3 4/47
6. FUNCTIONAL BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
WRITE
STATE
MACHING
(WSM)
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
ADDRESS
LATCH
AND
BUFFER
A0~A17
C E
BYT E
OE
W E
RES ET
PROGRAM / ERASE
HIGH VOLTAGE
F49L400U/BA
FLASH
ARRAY
Y-
D
E
C
O
D
E
R
X-
D
E
C
O
D
E
R
Y-PASS GATE
I / O BUFFER
DQ0~DQ14
DQ15 / A-1
ARRAY
SOURCE
HV
EFST
preliminary
F49L400UA/F49L400BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.3 5/47
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function of the device. The
F49L400UA/F49L400BA features various bus
operations as Table 3.
Table 3. F49L400UA/F49L400BA Operation Modes Selection
ADDRESS
DESCRIPTION
CE
OE WE
RESET
A17
|
A11
A10
A9
A8
|
A7
A6
A5
|
A2
A1 A0
DQ0~DQ7
Reset(3)
X
X
X
L, Vss
0.3V(3)
X
High Z
Read
L
L
H
H
AIN
Dout
Write
L
H
L
H
AIN
DIN
Output Disable
L
H
H
H
X
High Z
Standby
V
CC
0.3V
X
X
V
CC
0.3V
X
High Z
Sector Protect(2)
L
H
L
V
ID
SA
X
X
X
L
X
H
L
DIN
Sector Unprotect(2)
L
H
L
V
ID
SA
X
X
X
H
X
H
L
DIN
Temporary sector unprotect
X
X
X
V
ID
AIN
DIN
Auto-select
See Table 4
Notes:
1.
L= Logic Low = V
IL
, H= Logic High = V
IH
, X= Don't Care, SA= Sector Address, V
ID
=11.5V to 12.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3. See "Reset Mode" section.
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