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Datasheet: F49L004UA-70N (EliteMT (ESMT))

Org. = 512KbX8, Description = Flash 3.3V, Speed = 70/90 NS, Package = 32PLCC

 

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EFST
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 1/46
4 Mbit (512K x 8)
3V Only CMOS Flash Memory
1. FEATURES
!
Single supply voltage 2.7V-3.6V
!
Fast access time: 70/90 ns
!
Compatible with JEDEC standard
- Pinout, packages and software commands
compatible with single-power supply Flash
!
Low power consumption
- 20mA typical active current
- 0.2uA typical standby current
!
10,000 minimum program/erase cycles
!
Command register architecture
- Byte programming (9us typical)
- Sector Erase(sector structure: one 16 KB, two 8 KB,
one 32 KB, and seven 64 KB)
!
Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased
concurrently; Chip erase also provided.
- Automatically program and verify data at specified
address
!
Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
!
Ready/Busy (RY/BY )
- RY/
BY
output pin for detection of program or erase
operation completion
!
End of program or erase detection
- Data polling
- Toggle bits
!
Hardware reset
- Hardware pin( ESET
R
) resets the internal state machine
to the read mode
!
Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors
from a program or erase operation.
!
Low V
CC
Write inhibit is equal to or less than 2.0V
!
Boot Sector Architecture
- U = Upper Boot Sector
- B = Bottom Boot Sector
!
Packages available:
- 40-pin TSOPI
- 32-pin PLCC
2. ORDERING INFORMATION
Part No
Boot
Speed
Package
Part No
Boot
Speed
Package
F49L004UA-70T
Upper
70 ns
TSOPI
F49L004UA-90 T
Upper
90 ns
TSOPI
F49L004UA-70N
Upper
70 ns
PLCC
F49L004UA-90N
Upper
90 ns
PLCC
F49L004BA-70T
Bottom
70 ns
TSOPI
F49L004BA-90T
Bottom
90 ns
TSOPI
F49L004BA-70N
Bottom
70 ns
PLCC
F49L004BA-90N
Bottom
90 ns
PLCC
3. GENERAL DESCRIPTION
The F49L004UA/ F49L004BA is a 4 Megabit, 3V only
CMOS Flash memory device organized as 512K bytes of 8
bits. This device is packaged in standard 40-pin TSOP and
32-pin PLCC. It is designed to be programmed and erased
both in system and can in standard EPROM programmers.
With access times of 70 ns and 90 ns, the F49L004UA/
F49L004BA allows the operation of high-speed
microprocessors. The device has separate chip enable
CE, write enable WE , and output enable
OE
controls.
EFST's memory devices reliably store memory data even
after 100,000 program and erase cycles.
The F49L004UA/ F49L004BA is entirely pin and
command set compatible with the JEDEC standard for 4
Megabit Flash memory devices. Commands are written to
the command register using standard microprocessor write
timings.
The F49L004UA/ F49L004BA features a sector erase
architecture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64
Kbytes. Sectors can be erased individually or in groups
without affecting the data in other sectors. Multiple-sector
erase and whole chip erase capabilities provide the
flexibility to revise the data in the device.
The sector protect/unprotect feature disables both
program and erase operations in any combination of the
sectors of the memory. This can be achieved in-system or
via programming equipment.
A low V
CC
detector inhibits write operations on loss of
power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the
Toggle Bit I feature on DQ6. Once the program or erase
cycle has been successfully completed, the device
internally resets to the Read mode.
EFST
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 2/46
4. PIN CONFIGURATIONS
4.1 40-pin TSOP I
4.2 32-pin PLCC
4.3 Pin Description
Symbol
Pin Name
Functions
A0~A18
Address Input
To provide memory addresses.
DQ0~DQ7
Data Input/Output
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
CE
Chip Enable
To activate the device when CE is low.
OE
Output Enable
To gate the data output buffers.
WE
Write Enable
To control the Write operations.
RESET
Reset
Hardware Reset Pin/Sector Protect Unprotect (for 40-TSOP)
RY/ BY
Ready/Busy
To check device operation status(for 40 TSOP)
V
CC
Power Supply
To provide power
GND
Ground
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
A14
A13
A8
A9
A11
OE
A10
C E
DQ7
DQ
6
DQ
5
DQ
4
DQ
3
GN
D
DQ
2
DQ
1
32 31 30
A1
7
WE
V
CC
A1
8
A1
6
A1
5
A1
2
14 15 16 17 18 19 20
4 3 2 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
N C
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
A17
VSS
N C
N C
A10
DQ 7
DQ 6
DQ 5
DQ 4
VCC
VCC
N C
DQ 3
DQ 2
DQ 1
DQ 0
OE
VSS
CE
A0
EFST
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 3/46
5. SECTOR STRUCTURE
Table 1: F49L004UA Sector Address Table
Sector Address
Sector
Sector Size
(Kbytes)
Address range
A18
A17
A16
A15
A14
A13
SA10
16
7C000H-7FFFFH
1
1
1
1
1
X
SA9
8
7A000H-7BFFFH
1
1
1
1
0
1
SA8
8
78000H-79FFFH
1
1
1
1
0
0
SA7
32
70000H-77FFFH
1
1
1
0
X
X
SA6
64
60000H-6FFFFH
1
1
0
X
X
X
SA5
64
50000H-5FFFFH
1
0
1
X
X
X
SA4
64
40000H-4FFFFH
1
0
0
X
X
X
SA3
64
30000H-3FFFFH
0
1
1
X
X
X
SA2
64
20000H-2FFFFH
0
1
0
X
X
X
SA1
64
10000H-1FFFFH
0
0
1
X
X
X
SA0
64
00000H-0FFFFH
0
0
0
X
X
X
Table 2: F49L004BA Sector Address Table
Sector Address
Sector
Sector Size
(Kbytes)
Address range
A18
A17
A16
A15
A14
A13
SA10
64
70000H-7FFFFH
1
1
1
X
X
X
SA9
64
60000H-6FFFFH
1
1
0
X
X
X
SA8
64
50000H-5FFFFH
1
0
1
X
X
X
SA7
64
40000H-4FFFFH
1
0
0
X
X
X
SA6
64
30000H-3FFFFH
0
1
1
X
X
X
SA5
64
20000H-2FFFFH
0
1
0
X
X
X
SA4
64
10000H-1FFFFH
0
0
1
X
X
X
SA3
32
08000H-0FFFFH
0
0
0
1
X
X
SA2
8
06000H-07FFFH
0
0
0
0
1
1
SA1
8
04000H-05FFFH
0
0
0
0
1
0
SA0
16
00000H-03FFFH
0
0
0
0
0
X
EFST
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 4/46
6. FUNCTIONAL BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
WRITE
STATE
MACHING
(WSM)
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
ADDRESS
LATCH
AND
BUFFER
A0~A18
C E
OE
W E
RE SE T
(for40-TSOP)
PROGRAM / ERASE
HIGH VOLTAGE
F49L004U(B)A
FLASH
ARRAY
Y
-
D
E
CO
DE
R
X
-
D
E
CO
DE
R
Y-PASS GATE
I / O BUFFER
DQ0~DQ7
ARRAY
SOURCE
HV
EFST
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 5/46
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function of the device. The F49L004UA/
F49L004BA features various bus operations as
Table 3.
Table 3. F49L004UA/F49L004BA Operation Modes Selection
ADDRESS
DESCRIPTION
CE
OE WE
RESET
A18
|
A13
A12
|
A10
A9
A8
|
A7
A6
A5
|
A2
A1 A0
DQ0~DQ7
Reset(3)
X
X
X
L, Vss
0.3V(4)
X
High Z
Read
L
L
H
H
AIN
Dout
Write
L
H
L
H
AIN
DIN
Output Disable
L
H
H
H
X
High Z
Standby
V
CC
0.3V
X
X
V
CC
0.3V
X
High Z
Sector Protect(2)
L
H
L
V
ID
SA
X
X
X
L
X
H
L
DIN
Sector Unprotect(2)
L
H
L
V
ID
SA
X
X
X
H
X
H
L
DIN
Temporary sector unprotect
X
X
X
V
ID
AIN
DIN
Auto-select
See Table 4
Notes:
1.
L= Logic Low = V
IL
, H= Logic High = V
IH
, X= Don't Care, SA= Sector Address, V
ID
=11.5V to 12.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3. ESET
R
pin for 40-TSOP package type only.
4. See "Reset Mode" section.
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