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Datasheet: AL4V18x (AverLogic Technologies, Inc.)

1K X 18 and 4K X 18 Line Buffers


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Data Sheets
Version 2.0
AL4V183/AL4V185 February 20, 2003
11-07-01 Preliminary Version 1.0
09-13-02 1.
Revised Vp (Input Pin Voltage) in section 10.1 Absolute Maximum Ratings
Revised V
High Level Input Voltage in section 10.2 Recommended Operating
Changed the package support from TQFP to STQFP
Changed data sheets version to 2.0
02-20-03 Company Contact Information updated
AL4V183/AL4V185 February 20, 2003
AL4V183/AL4V185 (1k x18, 4k x18) 16K-Bit,
64K-Bit Line FIFO

1.0 Description _________________________________________________________________ 4
2.0 Features____________________________________________________________________ 4
3.0 Applications_________________________________________________________________ 5
4.0 Chip Information ____________________________________________________________ 5
4.1 Marking Information______________________________________________________________ 5
4.2 Ordering Information _____________________________________________________________ 5
5.0 Pin-out Diagram _____________________________________________________________ 5
6.0 Block Diagram ______________________________________________________________ 6
7.0 Pin Definition and Description _________________________________________________ 7
8.0 Memory Operations __________________________________________________________ 8
8.1 Inputs and Outputs _______________________________________________________________ 8
8.2 Controls _________________________________________________________________________ 8
9.0 Multiple Devices Bus Expansion _______________________________________________ 10
9.1 Width Expansion Configuration____________________________________________________ 10
10.0 Electrical Characteristics ____________________________________________________ 12
10.1 Absolute Maximum Ratings ______________________________________________________ 12
10.2 Recommended Operating Conditions ______________________________________________ 12
10.3 DC Characteristics ______________________________________________________________ 12
10.4 AC Electrical Characteristics _____________________________________________________ 13
10.5 Timing Diagrams __________________________________________________________ 14
11.0 Mechanical Drawing _______________________________________________________ 18
11.1 10x10mm 64-Pin STQFP Package _________________________________________________ 18
AL4V183/AL4V185 February 20, 2003
1.0 Description

The AL4V183 and AL4V185 series memory products are high-performance, low-power 18-bit
read/write FIFO (First-In-First-Out) memory chips. They are specially designed to buffer high
speed streaming data for a wide range of data buffering applications, such as optical disk data
caching, video line data buffering.

The 18-bit input and output ports operate independently at a maximum speed of 100MHz. The
built-in address decoder and pointer managing circuits provide a straightforward bus interface to
serially read/write memory that reduces inter-chip design efforts. The AL4V18x embedded memory
array and high performance process technologies with extended controller functions, such as read
skip, Bus-Matching and Endian Select, offer flexible memory management.

The input data is synchronous with a free-running clock (WCLK), and Write-Enable pins (/WEN).
Data is written into the FIFO on every clock when enable pins are asserted. The output is
synchronous with the other free-running clock (RCLK) and enables (/REN). An Output Enable
pin (/OE) is provided at the read port for tri-state control of the output port.

Bus-Matching feature can flexibly configure input and output bus width. The chip can
automatically convert the input data bus width to match up output data bus width by packing or
unpacking the data. A Big-Endian/Little-Endian data word format is provided to invert the read-in
bytes sequence for output. The AL4V18x series are operating in 3.3V power supply with 5V signal
tolerant input. These chips are available as a 64-pin STQFP Package.
2.0 Features
1,024 x18-bit cell array (AL4V183)
4,096 x18-bit cell array (AL4V185)
100 MHz Operation
10 ns read/write cycle time
Independent Read and Write operations
Output enable (data skipping)
User selectable input and output bus width
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x19 out
- x18 in to x18 out
Big/Little Endian word format selectable
3.3V power supply with 5V signal tolerant input
Available in a 64-pin Thin Quad Flat Pack (STQFP) packages
AL4V183/AL4V185 February 20, 2003
3.0 Applications
Video line data capture
Hard Disk cache memory
Anti-skip audio data buffer
Multimedia systems
Time base correction (TBC)
4.0 Chip Information
4.1 Marking Information
Part Number: X = 3, 5 as
AL4V183, AL4V185
Package: XX = TF:
Speed Grade: XX = -10
Version Number: X = A, B, C..
Lot Number
Date Code
4.2 Ordering Information
The ordering information for AL4V183 and AL4V185 are:
Part number
Power Supply
AL4V183 (A-10-TF)
64-pin plastic STQFP (14x14mm)
Sample in Nov., 2001
AL4V185 (A-10-TF)
64-pin plastic STQFP (14x14mm)
Sample in Nov., 2001

5.0 Pin-out Diagram
The AL4V183 and AL4V185 pin-out diagram is following:

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