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Datasheet: AL4CX293 (AverLogic Technologies, Inc.)

9-bit/18-bit Synchronous Fifo


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Data Sheets
Version 1.1
October 20, 2002
Preliminary Version 1.0
Release version 1.1. Company Contact Information updated
October 20, 2002
AL4CX293 (16K/32K/64K/128K x9,
8K/16K/32K/64K x18) Synchronous FIFO

1.0 Description _________________________________________________________________ 5
2.0 Features____________________________________________________________________ 6
3.0 Applications_________________________________________________________________ 6
4.0 Chip Information ____________________________________________________________ 6
4.1 Marking Information______________________________________________________________ 6
4.2 Ordering Information _____________________________________________________________ 7
5.0 Pin Diagram ________________________________________________________________ 7
6.0 Block Diagram ______________________________________________________________ 8
7.0 Pin Definition and Description _________________________________________________ 8
8.0 Function Description ________________________________________________________ 12
8.1 Timing Modes: Standard vs. First Word Fall Through (FWFT) Mode ____________________ 13
8.2 Standard Mode __________________________________________________________________ 14
8.3 First Word Fall Through Mode (FWFT)_____________________________________________ 15
8.4 Programmable Flag Loading ______________________________________________________ 16
8.5 Asynchronous and Synchronous Programmable Flag Timing Selection ___________________ 19
8.6 Serial Programming Mode ________________________________________________________ 20
8.7 Parallel Programming Mode_______________________________________________________ 20
8.8 Retransmit Operation ____________________________________________________________ 21
9.0 Memory Operations: _________________________________________________________ 23
9.1 Inputs and Outputs: ______________________________________________________________ 23
9.2 Controls: _______________________________________________________________________ 23
9.3 Flags Control: ___________________________________________________________________ 27
10.0 Multiple Devices Bus Expansion and Cascading _________________________________ 28
10.1 Width Expansion Configuration___________________________________________________ 28
10.2 Depth Expansion Configuration (FWFT Mode Only) _________________________________ 29
11.0 Electrical Characteristics ____________________________________________________ 32
October 20, 2002
11.1 Absolute Maximum Ratings ______________________________________________________ 32
11.2 Recommended Operating Conditions ______________________________________________ 32
11.3 DC Characteristics ______________________________________________________________ 32
11.4 AC Electrical Characteristics _____________________________________________________ 33
11.5 Timing Diagrams _______________________________________________________________ 35
12.0 Mechanical Drawing _______________________________________________________ 51
12.1 14x14mm 80-Pin TQFP Package __________________________________________________ 51
October 20, 2002
1.0 Description
The AL4CX263/AL4CX273/AL4CX283/AL4CX293 series products are high- performance, low-
power consumption 9bit or 18bit read/write synchronous FIFO (First-In-First-Out) memory chips.
They are specially designed to buffer high speed streaming data for a wide range of multimedia and
communication applications, such as optical disk controllers, Local Area Networks (LANs),
SONET(Synchronous Optical Network).

The AL4CX263/AL4CX273/AL4CX283/AL4CX293 FIFO (First In First Out) memory provides
completely independent 18bit bus width input and output port operation with flexible x18/ x9 Bus-
Matching data flow control at a maximum speed of 166Mhz. The products are available in
densities from 128Kbit to 1Mbit. Additional features of the AL4CX2x3 series include: fixed and
programmable flags; low first word latency; partial reset; Endian select; expandable depth/width
and optional first-word-fall-through.

The embedded memory array with built-in address decoder, pointer manager and state-of-the-art
circuits provide an easy-to-use interface to serial read/write memory and offer a flexible way to
manage memory in the system design.

The input port of the FIFO is controlled by a free running clock (WCLK), and an input enable
(/WEN). The output port is controlled by another clock (RCLK) and an output enable (/REN). Data
is read into or output from FIFO synchronous on every individual WRCK or RCLK clock cycle
when /WEN or /REN is asserted respectively.

These FIFOs support selectable bus width up to 18bit for both input and output ports and can be
configured as x18 to x18, x18 to x9, x9 to x18 and x9 to x9 multiple input and output port bus
width. This allows for easy conversion of the bus width between the input flow and output flow.

There are two fixed flags, Empty Flag/Output Ready and Full Flag/Input Ready, and two
programmable flags, Almost-Empty and Almost-Full. The flags enable further manipulation of the
synchronous control.

Multiple AL4CX2x3s can be cascaded to expand the storage depth or can be used in parallel to
expand bus width. The FIFOs are 3.3-volt devices with 5-volt input tolerance. And are available
in the 80-pin thin quad flat Pack (TQFP Package).
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