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Datasheet: AL4CS225 (AverLogic Technologies, Inc.)

18-bit Synchronous Fifo


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Data Sheets
Version 2.1
AL4CS205/AL4CS215/AL4CS225/AL4CS235/AL4CS245 February 20, 2003
07-10-01 Preliminary version 1.0
10-17-01 Version 1.1, Add DC and AC timing data
11-28-01 Version 1.2, modify 8.5 programmable timing selection
01-03-02 Version 2.0, add 2 synchronous modes support to Programmable Flag timing
selection table, change pin 49 definition from VCC to NC.
05-08-02 Speed grade information update
02-20-03 Company Contact Information updated
AL4CS205/AL4CS215/AL4CS225/AL4CS235/AL4CS245 February 20, 2003
AL4CS245 (256 x 18, 512 x18, 1k x 18, 2k x 18,
4k x 18) Synchronous FIFO

1.0 Description _________________________________________________________________ 5
2.0 Features____________________________________________________________________ 5
3.0 Applications_________________________________________________________________ 6
4.0 Chip Information ____________________________________________________________ 6
4.1 Marking Information______________________________________________________________ 6
4.2 Ordering Information _____________________________________________________________ 6
5.0 Pin Diagram ________________________________________________________________ 6
6.0 Block Diagram ______________________________________________________________ 7
7.0 Pin Definition and Description _________________________________________________ 8
8.0 Function Description ________________________________________________________ 10
8.1 Timing Modes: Standard vs First Word Fall Through (FWFT) Mode ____________________ 10
8.2 Standard Mode __________________________________________________________________ 11
8.3 First Word Fall Through Mode (FWFT)_____________________________________________ 12
8.4 Programmable Flag Loading ______________________________________________________ 13
8.5 Asynchronous and Synchronous Programmable Flag Timing Selection ___________________ 13
8.6 Register-Buffered Flag Output Selection_____________________________________________ 14
9.0 Memory Operations: _________________________________________________________ 15
9.1 Inputs and Outputs: ______________________________________________________________ 15
9.2 Controls: _______________________________________________________________________ 15
9.3 Flags and Cascading Controls: _____________________________________________________ 17
10.0 Multiple Devices Bus Expansion and Cascading _________________________________ 18
10.1 Width Expansion _______________________________________________________________ 19
10.2 Depth Expansion -- Daisy Chain (With Programmable Flags) _________________________ 19
10.3 Depth Expansion (FWFT Mode) __________________________________________________ 21
11.0 Electrical Characteristics ____________________________________________________ 23
11.1 Absolute Maximum Ratings ______________________________________________________ 23
AL4CS205/AL4CS215/AL4CS225/AL4CS235/AL4CS245 February 20, 2003
11.2 Recommended Operating Conditions ______________________________________________ 23
11.3 DC Characteristics ______________________________________________________________ 23
11.4 AC Electrical Characteristics _____________________________________________________ 24
11.5 Timing Diagrams _______________________________________________________________ 26
12.0 Mechanical Drawing _______________________________________________________ 37
12.1 10x10mm 64-Pin STQFP Package _________________________________________________ 37
12.2 14x14mm 64-pin TQFP Package __________________________________________________ 38
AL4CS205/AL4CS215/AL4CS225/AL4CS235/AL4CS245 February 20, 2003
1.0 Description

The AL4CS205/AL4CS215/AL4CS225/AL4CS235/AL4CS245 series products are high-
performance, low-power 18bit read/write synchronous FIFO (First-In-First-Out) memory chips.
They are specially designed to buffer high speed streaming data for a wide range of multimedia and
communication applications, such as optical disk controllers, Local Area Networks (LANs),
SONET (Synchronous Optical Network).

The input data is synchronous with a free-running clock (WCLK), and an input enable pin (/WEN).
Data is written into the FIFO on every write clock when /WEN is low. The output data is
synchronous with the other free-running clock (RCLK) and enable pin (/REN). Data is read out
from the FIFO on every read clock when both /REN and /OE are low. An Output Enable pin (/OE)
can control the output port becoming tri-state. The FIFOs provide 3 fixed flags, Empty
Flag<Output Ready> (/EF</OR>), Full Flag<Input Ready> (/FF/<IR>) and Half-Full flag (/HF),
and two programmable flags, Almost-Empty (/PAE) and Almost-Full (/PAF). The offsets of the
/PAE and /PAF flags are loaded when Load pin (/LD) goes low. A Half-Full flag (/HF) is available
in a single device configuration. Two timing modes are supported in the device: Standard Mode
and First Word Fall-Through (FWFT) mode. In Standard Mode, the first word written to an empty
FIFO will not appear on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating /REN and enabling a rising RCLK edge, will load the word
from internal memory to the data output port. In FWFT mode, the first word written to an empty
FIFO is clocked directly to the data output port after three transitions of the RCLK signal. A /REN
does not have to be low for accessing the first word.

These devices are depth and width expandable. The /WXI, /RXI, /WXO and /RXO pins are used to
expand multiple FIFOs using a Daisy-Chain technique.
2.0 Features
256 x18-bit memory array (AL4CS205)
512 x18-bit memory array (AL4CS215)
1,024 x18-bit memory array (AL4CS225)
2,048 x18-bit memory array (AL4CS235)
4,096 x18-bit memory array (AL4CS245)
133 MHz Operation
7.5 ns read/write cycle time
Independent Read and Write operations
Standard or First Word Fall Through mode
Single or double register-buffered Empty
and Full flags
Depth and width expandable
Programmable Almost-Empty and
Almost-Full flags
Half-Full flag
Output enable (data skipping)
3.3V power supply with 5V signal tolerant
Available in a 64-lead thin quad flat pack
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