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Datasheet: AL4CE215 (AverLogic Technologies, Inc.)

18-bit Synchronous Fifo

 

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AL4CE205
AL4CE215
AL4CE225
AL4CE235
AL4CE245
Data Sheets
Version 1.01

AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245 April 5, 2002
2
Amendments
01-04-02 Version 1.0
04-05-02 Update speed grade information
02-20-03 Company Contact Information updated
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245 April 5, 2002
3
AL4CE205/AL4CE215/AL4CE225/AL4CE235
/AL4CE245 (256 x 18, 512 x18, 1k x 18, 2k x
18, 4k x 18) Enhanced Synchronous FIFO

Contents:
1.0 Description _________________________________________________________________ 4
2.0 Features____________________________________________________________________ 4
3.0 Applications_________________________________________________________________ 5
4.0 Chip Information ____________________________________________________________ 5
4.1 Marking Information______________________________________________________________ 5
4.2 Ordering Information _____________________________________________________________ 5
5.0 Pin Diagram ________________________________________________________________ 5
6.0 Block Diagram ______________________________________________________________ 6
7.0 Pin Definition and Description _________________________________________________ 7
8.0 Function Description _________________________________________________________ 9
8.1 Operating Timing_________________________________________________________________ 9
8.2 Flags Status ______________________________________________________________________ 9
8.3 Programmable Flag Loading ______________________________________________________ 10
9.0 Memory Operations: _________________________________________________________ 11
9.1 Inputs and Outputs: ______________________________________________________________ 11
9.2 Controls: _______________________________________________________________________ 11
9.3 Flags Control: ___________________________________________________________________ 13
11.0 Electrical Characteristics ____________________________________________________ 15
11.1 Absolute Maximum Ratings ______________________________________________________ 15
11.2 Recommended Operating Conditions ______________________________________________ 15
11.3 DC Characteristics ______________________________________________________________ 15
11.4 AC Electrical Characteristics _____________________________________________________ 16
11.5 Timing Diagrams _______________________________________________________________ 18
12.0 Mechanical Drawing _______________________________________________________ 23
12.1 10x10mm 64-Pin STQFP Package _________________________________________________ 23
12.2 14x14mm 64-pin TQFP Package __________________________________________________ 24
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245 April 5, 2002
4
1.0 Description

The AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245 series products are high-
performance, low-power 18bit read/write synchronous FIFO (First-In-First-Out) memory chips.
They are specially designed to buffer high speed streaming data for a wide range of multimedia and
communication applications, such as optical disk controllers, Local Area Networks (LANs),
SONET (Synchronous Optical Network).

The input data is synchronous with a free-running clock (WCLK), and an input enable pin (/WEN).
Data is written into the FIFO on every write clock when /WEN is low. The output data is
synchronous with the other free-running clock (RCLK) and enable pin (/REN). Data is read out
from the FIFO on every read clock when both /REN and /OE are low. An Output Enable pin (/OE)
can control the output port becoming tri-state. The FIFOs provide 3 fixed flags, Empty
Flag<Output Ready> (/EF</OR>), Full Flag<Input Ready> (/FF/<IR>) and Half-Full flag (/HF),
and two programmable flags, Almost-Empty (/PAE) and Almost-Full (/PAF). The offsets of the
/PAE and /PAF flags are loaded when Load pin (/LD) goes low. A Half-Full flag (/HF) is available
in a single device configuration.

Bus-Matching feature can flexibly configure input and output bus width. The chip can
automatically convert the input data bus width to match up output data bus width by packing or
unpacking the data. A Big-Endian/Little-Endian data word format is provided to invert the read-in
bytes sequence for output. And the Retransmit function allows data to be reread from the FIFO
more than once.
2.0 Features
256 x18-bit memory array (AL4CE205)
512 x18-bit memory array (AL4CE215)
1,024 x18-bit memory array (AL4CE225)
2,048 x18-bit memory array (AL4CE235)
4,096 x18-bit memory array (AL4CE245)
133 MHz Operation
7.5 ns read/write cycle time
Independent Read and Write operations
Retransmit the data (reread the data)
User selectable input and output bus width
-
x9 in to x9 out
-
x9 in to x18 out
-
x18 in to x19 out
-
x18 in to x18 out
Big-Endian/Little-Endian word format
selectable
Double register-buffered Empty and Full
flags
Programmable Almost-Empty and
Almost-Full flags
Half-Full flag
Output enable (data skipping)
3.3V power supply with 5V input tolerant
Available in a 64-lead thin quad flat pack
(TQFP/STQFP)
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245
AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245 April 5, 2002
5
3.0 Applications
Routers
ATM switches
Cable modems
Wireless base stations
SONET(Synchronous Optical Network)
multiplexers
Multimedia systems
Time base correction (TBC)
4.0 Chip Information
4.1 Marking Information
AL4CE2x5
X-XX-XX
XXXX
XXXXX
Part Number: X = 0, 1, 2, 3, 4 as
AL4CE205, AL4CE215, AL4CE225,
AL4CE235, AL4CE245
Package: XX =
PF:
TQFP
TF:
STQFP
Speed Grade: XX = -10, -7.5
Version Number: X = A, B, C..
Lot Number
Date Code
4.2 Ordering Information
Two packages are available for AL4CE205/AL4CE215/AL4CE225/AL4CE235/AL4CE245.
Part number
Package
Power Supply
Status
AL4CE205/215/225/235/245 (A-7.5-PF)
64-pin plastic
TQFP(14x14mm)
+3.3V
10%
Sample in Nov.,2001
AL4CE205/215/225/235/245 (A-7.5-TF)
64-pin plastic
STQFP(10x10mm)
+3.3V
10%
Sample in Nov., 2001

5.0 Pin Diagram
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