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Datasheet: AL4CE211 (AverLogic Technologies, Inc.)

9-bit Synchronous Fifo

 

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AL4CE211
AL4CE221
AL4CE231
AL4CE241
AL4CE251
Data Sheets
Version 1.0
AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251
AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 February 20, 2003
2
Amendments
04-05-02 Preliminary Version 1.0
02-20-03 Company Contact Information updated
AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251
AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 February 20, 2003
3
AL4CE211/AL4CE221/AL4CE231/AL4CE241
/AL4CE251 (512 x9, 1k x9, 2k x9, 4k x9, 8k x9)
Enhanced Synchronous FIFO

Contents:
1.0 Description _________________________________________________________________ 4
2.0 Features____________________________________________________________________ 4
3.0 Applications_________________________________________________________________ 4
4.0 Chip Information ____________________________________________________________ 5
4.1 Marking Information______________________________________________________________ 5
4.2 Ordering Information _____________________________________________________________ 5
5.0 Pin-out Diagram _____________________________________________________________ 5
6.0 Block Diagram ______________________________________________________________ 6
7.0 Pin Definition and Description _________________________________________________ 6
8.0 Memory Operations __________________________________________________________ 8
8.1 Inputs and Outputs _______________________________________________________________ 8
8.2 Controls _________________________________________________________________________ 8
8.3 Flags___________________________________________________________________________ 10
9.0 Multiple Devices Bus Expansion and Cascading __________________________________ 10
9.1 Width Expansion Configuration____________________________________________________ 10
10.0 Electrical Characteristics ____________________________________________________ 12
10.1 Absolute Maximum Ratings ______________________________________________________ 12
10.2 Recommended Operating Conditions ______________________________________________ 12
10.3 DC Characteristics ______________________________________________________________ 12
10.4 AC Electrical Characteristics _____________________________________________________ 13
10.5 Timing Diagrams _______________________________________________________________ 14
11.0 Mechanical Drawing _______________________________________________________ 21
11.1 7x7mm 32-pin TQFP Package ____________________________________________________ 21
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4
1.0 Description

The AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 series memory products are high-
performance, low-power 9-bit read/write FIFO (First-In-First-Out) memory chips. They are
specially designed to buffer high speed streaming data for a wide range of communication
applications, such as optical disk controllers, Local Area Networks (LANs), SONET (Synchronous
Optical Network).

The input data is synchronous with a free-running clock (WCLK), and input-enable pins (/WEN).
Data is written into the FIFO on every clock when enable pins are asserted. The output is
synchronous with the other free-running clock (RCLK) and enables (/REN). An Output Enable
pin (/OE) is provided at the read port for tri-state control of the output port. The FIFOs can output
two fixed flags, Empty Flag( /EF) and Full Flag (/FF), and two programmable flags, Almost-Empty
(/PAE) and Almost-Full (/PAF). The offsets of the /PAE and /PAF flags are loaded when Load pin
(/LD) goes low.

The AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 series are enhanced version of the
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251 series with Retransmit function
supported which allows data to be reread from the FIFO more than once.
2.0 Features
512 x9-bit cell array (AL4CE211)
1,024 x9-bit cell array (AL4CE221)
2,048 x9-bit cell array (AL4CE231)
4,096 x9-bit cell array (AL4CE241)
8,192 x9-bit cell array (AL4CE251)
133 MHz Operation
7.5 ns read/write cycle time
Independent Read and Write operations
Retransmit the data (reread the data)
Empty and Full flags support
Programmable Almost-Empty and
Almost-Full flags
Output enable (data skipping)
3.3V power supply with 5V signal
tolerant input
Available in a 32-pin Thin Quad Flat
Pack (TQFP) packages
3.0 Applications
Routers
ATM switches
Cable modems
Wireless base stations
SONET(Synchronous Optical Network) multiplexers
Multimedia systems
Time base correction (TBC)
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5
4.0 Chip Information
4.1 Marking Information
AL4CE2X1
X-XX-XX
XXXX
XXXXX
Part Number: X = 1, 2, 3, 4, 5 as
AL4CS211, AL4CS221, AL4CS231,
AL4CS241, AL4CS251
Package: XX =
PF:
TQFP
Speed Grade: XX = -7.5, ..
Version Number: X = A, B, C..
Lot Number
Date Code
4.2 Ordering Information
The ordering information for AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 are:
Part number
Package
Power Supply
Status
AL4CE211/221/231/241/251(A-7.5-PF)
32-pin plastic
TQFP(7x7mm)
+3.3V
10%
Sample in Aug., 2001

5.0 Pin-out Diagram
The AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 pin-out diagram is following:
TQFP PACKAGE TOP VIEW
AVERLOGIC
AL4CE2x1
x-xx-xx
xxxx
xxxx
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
/FF
Q0
Q1
Q2
Q3
/OE
/EF
Q4
16
15
14
13
12
11
10
9
D2
D3
D7
/RS
D8
D4
D5
D6
25
26
27
28
29
30
31
32
/WEN
WCLK
/RT
VCC
Q8
Q7
Q6
Q5
D1
D0
/PAF
/PAE
GND
/REN
RCLK
/LD
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6.0 Block Diagram
(512, 1k ,2k,
4k, 8k) x9
Memory
Array
Input
Buffer
Output
Buffer
Write
Control
Logic
Read
Control
Logic
Flag Logic
Write Pointer
Read Pointer
Offset
Regissers
Reset Logic
Input data bus
Output data bus
/OE
WCLK
/WEN
/LD
/RS
RCLK
/REN
/FF
/EF
/PAF
/PAE
Figure 1. AL4CE2x1 FIFO Block Diagram
/RT

The internal structure of the AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 consists of
Input/Output buffers, Read/Write Control Logic and main (512, 1k, 2k, 4k, 8k) x9 different
configuration memory cell array and state-of-the-art logic design that takes care of addressing and
controlling the read/write data.
7.0 Pin Definition and Description
The pin-out definition and function are described as following:

Write Bus Signals
Pin
Symbol
Pin name
TQFP
Pin no.
I/O
Typ
Description
D[8:0]
Data Inputs [26:32], 1, 2 I 9-bit input data bus.
/WEN
Write Enable 24
I When /WEN is LOW, data is written into the FIFO on
every rising edge of WCLK. When /WEN is HIGH,
the FIFO holds the previous data. Data will not be
written into the FIFO if the /FF is LOW.
WCLK Write Clock 23
I Data is written into the FIFO on a rising edge of
WCLK when the Write Enable(s) are asserted. Data
will not be written into FIFO if /FF is not LOW.
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7
Read Bus Signals
Pin
symbol
Pin name
TQFP
Pin no.
I/O
typ
Description
Q[8:0]
Data Outputs [20:12]
O 9-bit output data bus.
/REN
Read Enable 6
I When both /REN are LOW, data is read from the
FIFO on every rising edge of RCLK. Data will not be
read from the FIFO if the /EF is LOW.
/OE
Output
Enable
9
I When /OE is LOW, the data output bus is active. If
/OE is HIGH, the output data bus will be in high-
impedance.
RCLK
Read Clock 7
I Data is read from the FIFO on a rising edge of RCLK
when /REN is LOW, and if the FIFO is not empty.

Miscellaneous & Flags Signals
Pin
Symbol
Pin name
TQFP
Pin no.
I/O
typ
Description
/RS
Reset
25
I When /RS is set LOW, internal read and write
pointers are set to the first location of the RAM array,
/FF and /PAF go HIGH, and /PAE and /EF go LOW.
A reset is required before an initial WRITE after
power-up.
/LD
Load
8
When /LD is LOW, data on the inputs D0D11 is
written to the offset and depth registers on the rising
edge of the WCLK, when /WEN is LOW. When /LD
is LOW, data on the outputs Q0Q11 is read from the
offset and depth registers on the rising edge of the
RCLK, when /REN is LOW.
/RT
Retransmit 22
/RT asserted on the rising edge of RCLK initialized
the READ pointer to zero, sets the /EF flag to LOW
and does not affect the write pointer, programming
/FF
Full Flag 11
O /FF indicates whether or not the FIFO memory is full.
/EF
Empty Flag 10
O /EF indicates whether or not the FIFO memory is
empty.
/PAE
Programmab
le Almost-
Full Flag
4
O When /PAE is LOW, the FIFO is Almost-Empty
based on the offset programmed into the FIFO.
/PAF
Programmab
le Almost-
Full Flag
3
O When /PAF is LOW, the FIFO is Almost Full based
on the offset programmed into the FIFO.
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AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 February 20, 2003
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Power/Ground Signals
Pin
Symbol
Pin name
TQFP
Pin no.
I/O
typ
Description
VCC
Power
21
- 3.3V
10% power supply
GND
Ground
5
- Ground.
8.0 Memory Operations
8.1 Inputs and Outputs
8.1.1 DATA INPUTS (D8
~
D0)
D8 ~ D0 are 9-bit wide of input data port.

8.1.2 DATA OUTPUTS (Q8-Q0)
Q8 ~ Q0 are 9-bit wide of output data port.
8.2 Controls
8.2.1 Reset (/RS)
Reset takes place when the Reset (/RS) input is LOW. During reset, both internal read and write
pointers are set to the staring position. A reset is required to initial internal logic after power-up. The
Full Flag (/FF) and Programmable Almost-Full Flag (/PAF) will be reset to HIGH after t
RSF
. The
Empty Flag (/EF) and Programmable Almost-Empty Flag (/PAE) will be reset to LOW after t
RSF
.
During reset, the output register is initialized to all zeros and the offset registers are initialized to their
default values.

8.2.2 Write Clock (WCLK)
A write cycle is initiated on the rising edge of the Write Clock (WCLK). Data setup and hold times
must be met with respect to the rising edge of WCLK. The Full Flag (/FF) and Programmable
Almost-Full Flag (/PAF) are synchronized with respect to the rising edge of the Write Clock
(WCLK).
The Write and Read Clocks can be asynchronous or coincident.

8.2.3 Write Enable1 (/WEN)
When Write Enable (/WEN) is low, data can be written into the input register and memory array on
the rising edge of every Write Clock (WCLK). Data is stored in the memory array sequentially and
independently of any on going read operation. When Write Enable (/WEN) is HIGH, the input holds
the previous data and no new data can be written into the memory array. To prevent data overflow,
the Full Flag (/FF) will go LOW, inhibiting further write operations. Upon the completion of a valid
read cycle, the Full Flag (/FF) will go HIGH after t
WFF
, allowing a valid write to begin. Write
Enable(s) are ignored when the FIFO is full.

8.2.4 Read Clock (RCLK)
Data can be read on the outputs on the rising edge of the Read Clock (RCLK), when all the output
controls /REN, Output Enable (/OE) are set LOW. The Empty Flag (/EF) and Programmable Almost-
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Empty Flag (/PAE) are synchronized with respect to the rising edge of the Read Clock (RCLK). The
Write and Read Clocks can be asynchronous or coincident.

8.2.5 Read Enable (/REN)
When Read Enables (/REN) is LOW, data is read from the memory array to the output register on the
rising edge of the Read Clock (RCLK) if the FIFO is not empty. When Read Enable (/REN) is
HIGH, the output register holds the previous data and no new data can to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (/EF) will go LOW, inhibiting further
read operations. Once a valid write operation has been done, the Empty Flag (/EF) will go HIGH
after t
REF
and a valid read can begin. The /EF flag is updated on the rising edge of RCLK. The Read
Enables (/REN) are ignored when the FIFO is empty.

8.2.6 Output Enable (/OE)
When Output Enable (/OE) is enabled (LOW), the parallel output buffers receive data from the output
register. When /OE is disabled (HIGH), the Q8 ~ Q0 output data bus is in a high-impedance state.

8.2.7 Load (/LD)
The AL4CE211/221/231/241/251 devices contain four 8-bit offset registers, which can be loaded
with data on the inputs, or read from the outputs. See following table for details of the size of the
registers and the default values.
1
st
word
2
nd
word
3
rd
word
4
th
word
[7:0] Empty Offset (LSB)
[0] Empty Offset (MSB)
[7:0] Full Offset (LSB)
[0] Full Offset (MSB)
AL4CE211
Default = 07h
Default = 0b
Default = 07h
Default = 0b
[7:0] Empty Offset (LSB)
[1:0] Empty Offset (MSB)
[7:0] Full Offset (LSB)
[1:0] Full Offset (MSB)
AL4CE221
Default = 07h
Default = 00b
Default = 07h
Default = 00b
[7:0] Empty Offset (LSB)
[2:0] Empty Offset (MSB)
[7:0] Full Offset (LSB)
[2:0] Full Offset (MSB)
AL4CE231
Default = 07h
Default = 000b
Default = 07h
Default = 000b
[7:0] Empty Offset (LSB)
[3:0] Empty Offset (MSB)
[7:0] Full Offset (LSB)
[3:0] Full Offset (MSB)
AL4CE241
Default = 07h
Default = 0000b
Default = 07h
Default = 0000b
[7:0] Empty Offset (LSB)
[4:0] Empty Offset (MSB)
[7:0] Full Offset (LSB)
[4:0] Full Offset (MSB)
AL4CE251
Default = 07h
Default = 00000b
Default = 07h
Default = 00000b


When the Write Enable1 (/WEN) and Load (/LD) are set LOW, data on the inputs D8 ~ D0 is written
into the Empty (Least Significant Bit) Offset register on the first rising edge of the Write Clock
(WCLK). Data is written into the Empty (Most Significant Bit) Offset register on the second rising
edge of the Write Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth transition. The fifth
transition of the Write Clock (WCLK) again writes to the Empty (Least Significant Bit) Offset
register.

However, writing all offset registers does not have to occur consecutively. The FIFO can return to
normal read/write operation by bringing the Load (/LD) pin HIGH after one or two offset registers
can be written. When the Load (/LD) pin is set LOW again, and Write Enable (/WEN) is LOW, the
next offset register in sequence is written.
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10
8.2.8 Retransmit (/RT)
The Retransmit operation can do multiple data read. The Retransmit operation occurs when a /RT
low is sampled at the rising edge of the RCLK. The read pointer will be reset to first location of the
memory and /EF will be brought to low (if /EF was HIGH before setup), and then the data can be read
out from the memory, starting at the beginning of the memory.
8.3 Flags

8.3.1 Full Flag (/FF)
The Full Flag (/FF) will go LOW, inhibiting further write operation, when the device is full. If no
reads are performed after Reset (/RS), the Full Flag (/FF) will go LOW after 512 writes for the
AL4CE211, 1,024 writes for the AL4CE221, 2,048 writes for the AL4CE231, 4,096 writes for the
AL4CE241 and 8,192 writes for the AL4CE251. The Full Flag (/FF) is synchronized with respect to
the rising edge of the Write Clock (WCLK).

8.3.2 Empty Flag (/EF)
The Empty Flag (/EF) will go LOW, inhibiting further read operations, when the read pointer is equal
to the write pointer, indicating the device is empty. The Empty Flag (/EF) is synchronized with
respect to the rising edge of the Read Clock (RCLK).

8.3.3 Programmable Almost- Full Flag (/PAF)
The Programmable Almost-Full flag (/PAF) will go LOW when the FIFO reaches the almost-full
condition. If no reads are performed after Reset (/RS), the Programmable Almost-Full flag (/PAF)
will go LOW after (512-m) writes for the AL4CE211, (1,024-m) writes for the AL4CE221, (2,048-m)
writes for the AL4CE231, (4,096-m) writes for the AL4CE241 and (8,192-m) writes for the
AL4CE251. The offset "m" is defined in the Full Offset registers. If there is no full offset specified,
the Programmable Almost-Full flag (/PAF) will go LOW at Full-7 words. The Programmable
Almost-Full flag (/PAF) is synchronized with respect to the rising edge of the Write Clock (WCLK).

8.3.4 Programmable Almost-Empty Flag (/PAE)
The Programmable Almost-Empty flag (/PAE) will go LOW when the read pointer is "n+1" locations
less than the write pointer. The offset "n" is defined in the Empty Offset registers. If no reads are
performed after Reset the Programmable Almost-Empty flag (/PAE) will go HIGH after "n+1" for the
AL4CE211/221/231/241/251. If there is no empty offset specified, the Programmable Almost-Empty
flag (/PAE) will go LOW at Empty+7 words. The Programmable Almost-Empty flag (/PAE) is
synchronized with respect to the rising edge of the Read Clock (RCLK).
9.0 Multiple Devices Bus Expansion and Cascading
9.1 Width Expansion Configuration

Simply connecting the corresponding input controls signals of multiple devices may increase data bus
width. A composite flag should be created for each of the end-point status flags (/EF and /FF). The
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11
partial status flags (/PAE and /PAF) can be detected from any one device. Figure 15 demonstrates an
18-bit word width data bus by using two AL4CE211/221/231/241/251s. Any word width expansion
can be attained by adding additional AL4CE211/221/231/241/251s.

AL4CE2x1
/WEN
WCLK
Q[8:0]
/PAE
RCLK
/REN
/OE
/RS
/FF
/PAF
/EF
D[8:0]
AL4CE2x1
/WEN
WCLK
Q[8:0]
/PAE
RCLK
/REN
/OE
/RS
/FF
/PAF
/EF
D[8:0]
Write Clock
Write Enable
Programmable
Write Controls
Write Controls
Read Controls
Read Clock
Read Enable
Output Enable
Programmable
Read Controls
Empty Flag/
Output Ready
18-Bit Data In Bus
18-Bit Data Out Bus
Full Flag/
Input Ready
Reset
Reset
9-Bit
9-Bit
Figure 2. Multiple FIFO memory
in bus width expansion



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12
10.0 Electrical Characteristics
10.1 Absolute Maximum Ratings
Parameter
3.3V Rating
Unit
V
DD
Supply Voltage
-0.3 ~ +3.8
V
V
P
Pin Voltage
-0.3 ~ +(V
DD
+0.3)
V
I
O
Output Current
-20 ~ +20
mA
T
AMB
Ambient Op. Temperature
0 ~ +85
C
T
stg
Storage temperature
-40 ~ +125
C

10.2 Recommended Operating Conditions
3.3V Rating
Parameter
Min
Typ
Max
Unit
V
DD
Supply Voltage
+3.0
+3.3
+3.6
V
V
IH
High Level Input Voltage
0.7 V
DD
V
DD
V
V
IL
Low Level Input Voltage
0
0.3 V
DD
V

10.3 DC Characteristics
(
V
DD
= 3.3V, Vss=0V.
T
AMB
= 0 to 70C)
3.3V Rating
Parameter
Min
Typ
Max
Unit
I
DD
Operating Current @20MHz
-
-
16
mA
I
DDS
Standby Current
-
1.8
5
mA
V
OH
Hi-level Output Voltage
2.4
-
V
DD
V
V
OL
Lo-level Output Voltage
-
-
+0.4
V
I
LI
Input Leakage Current
-2
-
+2
A
I
LO
Output Leakage Current
-10
-
+10
A
Note: The Operating Current is tested at RCLK=WCLK=20MHz and data inputs switch at
10MHz
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10.4 AC Electrical Characteristics
(
V
DD
= 3.3V, Vss=0V, T
AMB
= 0 to 70C)
133Mhz
Symbol
Parameter
Min
Max
Unit
t
S
Clock Cycle Frequency
-
133
MHz
t
A
Data Access Time
2
5
ns
t
CLK
Clock Cycle Time
7.5
-
ns
t
CLKH
Clock HIGH Time
3.5
-
ns
t
CLKL
Clock LOW Time
3.5
-
ns
t
DS
Data Setup Time
2.5
-
ns
t
DH
Data Hold Time
0.5
-
ns
t
ENS
Enable Setup Time
2.5
-
ns
t
ENH
Enable Hold Time
0.5
-
ns
t
RS
Reset Pulse Width
7.5
-
ns
t
RSS
Reset Setup Time
6
-
ns
t
RSR
Reset Recovery Time
6
-
ns
t
RSF
Reset to Flag and Output Time
-
9
ns
t
OLZ
Output Enable to Output in Low-Z
0
-
ns
t
OE
Output Enable to Output Valid
-
5
ns
t
OHZ
Output Enable to in High-Z
-
5
ns
t
WFF
Write Clock to Full Flag
-
5
ns
t
REF
Read Clock to Empty Flag
-
5
ns
t
AF
Write Clock to Almost-Full Flag
-
5
ns
t
AE
Read Clock to Almost-Empty Flag
-
5
ns
t
SKEW1
Skew time between Read Clock & Write Clock
for /FF & /EF
3
-
ns
T
SKEW2
Skew time between Read Clock & Write Clock
for /PAE and /PAF
8
-
ns


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14
10.5 Timing Diagrams
/FF,/PAF
/EF,/PAE
Q0~A8
Figure 3. Reset Timing
/RS
/REN
/WEN
/LD
t
RSF
t
RSF
t
RSF
/OE = 1
/OE = 0
t
RS
t
RSR
t
RSS
t
RSR
t
RSR
t
RSS
t
RSS

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15
RCLK
/REN
/EF
Q0 ~ Q8
/OE
WCLK
t
CLK
t
CLKL
t
CLKH
Figure 4. Read Cycle Timing
/WEN
Valid Data
t
SKEW1
t
OE
t
OLZ
t
OHZ
t
A
t
REF
t
ENH
t
ENS
t
REF
No Operation

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16
Q0 ~ Q8
/OE
Figure 5. First Data Word Latency Timing
WCLK
D0 ~ D8
/WEN
RCLK
/EF
/REN
t
FRL
t
SKEW1
D0
D1
D2
D3
D4
D0
D1
t
DS
t
ENS
t
REF
t
ENS
t
A
t
A
t
OE
t
OLZ

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17
/OE
Q0 ~ Q8
Figure 6. Full Flag Timing
WCLK
D0 ~ D8
/FF
RCLK
/REN
Data Read
Next Data
t
SKEW1
Data in Output Buffer
Data Write
Data
Write
t
WFF
t
DS
t
WFF
t
SKEW1
t
WFF
t
DS
t
ENS
t
ENH
t
A
t
ENS
t
ENH
t
A
/WEN
t
ENH
t
ENS

AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251
AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 February 20, 2003
18
/OE
Q0 ~ Q8
Figure 7. Empty Flag Timing
WCLK
D0 ~ D8
/WEN
RCLK
/EF
/REN
t
ENS
Data in Output Buffer
Data Write
t
ENH
t
DS
t
ENS
t
ENH
t
SKEW1
t
DS
t
A
t
REF
t
REF
Data Write
Data Read
t
FRL
t
REF
t
SKEW1
t
FRL

/WEN
D0 ~ D7
Figure 8. Write Offset Registers
WCLK
/LD
PAE Offset
(LSB)
t
DS
PAE Offset
(MSB)
PAF Offset
(LSB)
t
ENS
t
ENH
t
DH
PAF Offset
(MSB)
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AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251 February 20, 2003
19
/REN
Q0 ~ Q7
Figure 9. Read Offset Registers Timing
RCLK
/LD
Data Output
PAF Offset
t
ENS
t
ENH
t
A
Empty Offset
(LSB)
Empty Offset
(MSB)
Full Offset
(LSB)
Full Offset
(MSB)


/PAE
RCLK
Figure 10. Programmable Empty Flag Timing
WCLK
/WEN
t
ENS
t
ENH
/REN
n words in FIFO
n+1 words in FIFO
t
ENS
t
ENH
t
PAES
t
SKEW2
t
PAES
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20
/PAF
RCLK
Figure 11. Programmable Full Flag Timing
WCLK
/WEN
t
ENS
t
ENH
/REN
t
ENS
t
ENH
Full - (m + 1) words in FIFO
Full - m words in FIFO
t
PAFS
t
PAFS
t
SKEW2




AL4CE211/AL4CE221/AL4CE231/AL4CE241/AL4CE251
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21
11.0 Mechanical Drawing
11.1 7x7mm 32-pin TQFP Package



CONTACT INFORMATION
Averlogic Technologies Corp.
4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan
Tel: +886 2-27915050
Fax: +886 2-27912132
E-mail:
sales@averlogic.com.tw
URL:
http://www.averlogic.com.tw

Averlogic Technologies, Inc.
90 Great Oaks Blvd. #204, San Jose, CA 95119
USA
Tel: 1 408 361-0400
Fax: 1 408 361-0404
E-mail:
sales@averlogic.com
URL:
http://www.averlogic.com
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