HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: AL422B (AverLogic Technologies, Inc.)

3M-bits FIFO Field Memory

 

Скачать: PDF   ZIP
 














AL422B Data Sheets
(Revision V1.3)
AL422B
AL422B February 20, 2003
2
Amendments
(Since April 2, 1999)
05-13-99 DC/AC characteristics (including current consumption) updated.
07-02-99 Pinout diagram (5.0) and DC external load (7.4) modified.
08-03-99 Description about TST pin added in sections 6.0 & 8.1.
09-02-99 8.3.2 Rewritten.
10-26-99 Capacitance provided in the AC characteristics section.
12-15-99 Remove TST pin restriction.
01-18-01 1.
Revised section "8.3.2 Read Enable during Reset Cycles" to "8.3.2 The Proper
Manipulation of FIFO Access".
2.
Add section "8.3.3 Single Field Write with Multiple Read Operation"
3.
Add section "8.3.4 One Field Delay Line (The Old Data Read)"
02-28-02 Address and version update
03-20-02 Correct Pin-out diagram
02-20-03 Company Contact Information updated
AL422B
AL422B February 20, 2003
3
AL422B
3M-Bits FIFO Field Memory

Contents:
1.0 Description _________________________________________________________________ 4
2.0 Features____________________________________________________________________ 4
3.0 Applications_________________________________________________________________ 4
4.0 Ordering Information _________________________________________________________ 4
5.0 Pinout Diagram______________________________________________________________ 5
6.0 Pin Description ______________________________________________________________ 5
7.0 Electrical Characteristics ______________________________________________________ 6
7.1 Absolute Maximum Ratings ________________________________________________________ 6
7.2 Recommended Operating Conditions ________________________________________________ 6
7.3 DC Characteristics ________________________________________________________________ 6
7.4 AC Characteristics ________________________________________________________________ 7
7.5 Timing Diagrams _________________________________________________________________ 9
8.0 Functional Description _______________________________________________________ 13
8.1 Memory Operation_______________________________________________________________ 14
8.2 Pin 19 Connection _______________________________________________________________ 15
8.3 Application Notes ________________________________________________________________ 15
8.3.1 Irregular Read/Write ___________________________________________________________________ 15
8.3.2 The Proper Manipulation of FIFO Access __________________________________________________ 16
8.3.3 Single Field Write with Multiple Read Operation ____________________________________________ 17
8.3.4 One Field Delay Line (The Old Data Read) _________________________________________________ 17
9.0 Mechanical Drawing ________________________________________________________ 19
AL422B
AL422B February 20, 2003
4
1.0 Description

The AL422B consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first
in first out). The interface is very user-friendly since all complicated DRAM operations are already
managed by the internal DRAM controller.

Current sources of similar memory (field memory) in the market provide limited memory size
which is only enough for holding one TV field, but not enough to hold a whole PC video frame
which normally contains 640x480 or 720x480 bytes. The AverLogic AL422B provides 50% more
memory to support high resolution for digital PC graphics or video applications. The 50% increase
in speed also expands the range of applications.
2.0 Features
384K (393,216) x 8 bits FIFO organization
Support VGA, CCIR, NTSC, PAL and
HDTV resolutions
Independent read/write operations (different
I/O data rates acceptable)
High speed asynchronous serial access
Read/write cycle time: 20ns
Access time: 15ns
Output enable control (data skipping)
Self refresh
3.3V power supply with 5V signal input
tolerant
Standard 28-pin SOP package
3.0 Applications
Multimedia systems
Video capture systems
Video editing systems
Scan rate converters
TV's picture in picture feature
Time base correction (TBC)
Frame synchronizer
Digital video camera
Buffer for communications systems




4.0 Ordering Information
Part number
Package
Power Supply
Status
AL422B
28-pin plastic SOP
+3.3 volt
Shipping
AL422B
AL422B February 20, 2003
5
5.0 Pin-Out Diagram
6.0 Pin Description
Pin name
Pin #
I/O type
Function
DI0~DI7
1~4, 11~14
input
Data input
WCK
9
Input
Write clock
/WE
5
Input (active low)
Write enable
/WRST
8
Input (active low)
Write reset
DO0~DO7
15~18, 25~28
Output (tristate)
Data output
RCK
20
Input
Read clock
/RE
24
Input (active low)
Read enable
/RRST
21
Input (active low)
Read reset
/OE
22
Input (active low)
Output enable
TST
7
Input
Test pin (pulled-down)*
VDD
10
3.3V
DEC/VDD
19
Decoupling cap input
GND
6, 23
Ground
AVERLOGIC
AL422B
XXXXX
XXXX
Lot Number
Date Code
DI0
DI
1
DI
2
DI
3
/WE
GND
TST
/WRST
WCK
VDD
DI
4
DI
5
DI
6
DI
7
D
O
0
D
O1
D
O2
D
O3
/RE
GND
/OE
/RRST
RCK
DEC
D
O4
D
O5
D
O6
D
O7
28
27
26
25
24
2
3
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AL422B
AL422B February 20, 2003
6
7.0 Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter
Ratings (3.3V)
Unit
V
DD
Supply Voltage
-1.0 ~ +4.5
V
V
P
Pin Voltage
-1.0 ~ +5.5
V
I
O
Output Current
-20 ~ +20
mA
T
AMB
Ambient Op. Temperature
0 ~ +70
C
T
stg
Storage temperature
-55 ~ +125
C

7.2 Recommended Operating Conditions
3.3V application
Parameter
Min
Max
Unit
V
DD
Supply Voltage
+3.0
+3.6
V
V
IH
High Level Input Voltage
+2.0
+5.5
V
V
IL
Low Level Input Voltage
-1.0
+0.8
V

7.3 DC Characteristics
(
V
DD
= 3.3V, Vss=0V.
T
AMB
= 0 to 70C)
3.3V application
Parameter
Min
Typ
Max
Unit
I
DD
Operating Current @20MHz
-
33
-
mA
I
DD
Operating Current @30MHz
-
45
-
mA
I
DD
Operating Current @40MHz
-
57
-
mA
I
DD
Operating Current @50MHz
-
68
-
mA
I
DDS
Standby Current
-
7
-
mA
V
OH
Hi-level Output Voltage
0.7V
DD
-
V
DD
V
V
OL
Lo-level Output Voltage
-
-
+0.4
V
I
LI
Input Leakage Current
-10
-
+10
A
I
LO
Output Leakage Current
-10
-
+10
A
AL422B
AL422B February 20, 2003
7
7.4 AC Characteristics
(
V
DD
= 3.3V, Vss=0V, T
AMB
= 0 to 70C)
3.3V application
Parameter
Min
Max
Unit
T
WC
WCK Cycle Time
20
1000
ns
T
WPH
WCK High Pulse Width
7
-
ns
T
WPL
WCK Low Pulse Width
7
-
ns
T
RC
RCK Cycle Time
20
1000
ns
T
RPH
RCK High Pulse Width
7
-
ns
T
RPL
RCK Low Pulse Width
7
-
ns
T
AC
Access Time
-
15
ns
T
OH
Output Hold Time
4
-
ns
T
HZ
Output High-Z Setup Time
3
15
ns
T
LZ
Output Low-Z Setup Time
3
15
ns
T
WRS
/WRST Setup Time
5
-
ns
T
WRH
/WRST Hold Time
2
-
ns
T
RRS
/RRST Setup Time
5
-
ns
T
RRH
/RRST Hold Time
2
-
ns
T
DS
Input Data Setup Time
5
-
ns
T
DH
Input Data Hold Time
2
-
ns
T
WES
/WE Setup Time
5
-
ns
T
WEH
/WE Hold Time
2
-
ns
T
WPW
/WE Pulse Width
10
-
ns
T
RES
/RE Setup Time
5
-
ns
T
REH
/RE Hold Time
2
-
ns
T
RPW
/RE Pulse Width
10
-
ns
T
OES
/OE Setup Time
5
-
ns
T
OEH
/OE Hold Time
2
-
ns
T
OPW
/OE Pulse Width
10
-
ns
T
TR
Transition Time
2
20
ns
C
I
Input Capacitance
-
7
pF
C
O
Output Capacitance
-
7
pF
Input voltage levels are defined as VIH=3.0V and VIL=0.4V.
AL422B
AL422B February 20, 2003
8
The read address needs to be at least 128 cycles after the write address.


DO external load:
AL422B
AL422B February 20, 2003
9
7.5 Timing Diagrams




cycle n
Reset
cycle (s)
cycle 0
cycle 1
WCK
/WRST
DI7~0
AL422-05 Write Cycle Timing (Write Reset)
T
TR
T
WRS
T
WRH
n-1
n
0
1
T
DS
T
DH
/WE = "L"
RCK
/RRST
DO7~0
n-1
n
T
OH
AL422-07 Read Cycle Timing (Read Reset)
T
RPH
T
RPL
0
1
cycle n
Reset
cycle (s)
cycle 0
cycle 1
T
RRS
T
RRH
T
AC
0
/RE = /OE = "L"
AL422B
AL422B February 20, 2003
10









cycle n
cycle n+1
cycle n+3
RCK
/OE
DO7~0
n-1
n
AL422-09 Read Cycle Timing (Output Enable)
T
RPH
T
RPL
T
OES
T
OEH
T
RC
n+1
T
OPW
T
OH
T
AC
cycle n+2
Hi-Z
cycle n+4
n+4
T
HZ
T
LZ
/RE = "L"
cycle n
cycle n+1
Disable cycle (s)
RCK
/RE
DO7~0
n-1
n
AL422-08 Read Cycle Timing (Read Enable)
T
RPH
T
RPL
T
RES
T
REH
T
RC
n+1
T
RPW
T
OH
T
AC
n+2
cycle n+2
/OE = "L"
AL422B
AL422B February 20, 2003
11




cycle n
cycle n+1
Disable cycle (s)
WCK
/WE
DI7~0
n-1
n
T
DS
T
DH
AL422-06 Write Cycle Timing (Write Enable)
T
WPH
T
WPL
T
WES
T
WEH
T
WC
n+1
n+2
T
WPW
cycle n+2
cycle n
cycle n+1
Disable cycle (s)
RCK
/RE
DO7~0
n-1
n
AL422-14 Read Cycle Timing (RE, RRST)
T
RPH
T
RPL
T
RES
T
REH
T
RC
n+1
T
RPW
T
OH
T
AC
0
T
RRS
T
RRH
/RRST
cycle 0
/OE = "L"
AL422B
AL422B February 20, 2003
12



cycle n
cycle n+1
Disable cycle (s)
WCK
/WE
DI7~0
n-1
n
T
DS
T
DH
AL422-15 Write Cycle Timing (WE, WRST)
T
WPH
T
WPL
T
WES
T
WEH
T
WC
n+1
1
T
WPW
cycle 0
T
WRS
T
WRH
/WRST
0
cycle 1
AL422B
AL422B February 20, 2003
13
8.0 Functional Description
The AL422B is a video frame buffer consisting of DRAM that works like a FIFO which is long
enough to hold up to 819x480 bytes of picture information and fast enough to operate at 50MHz. The
functional block diagram is as follows:
The I/O pinouts and functions are described as follows:
DI7~DI0 Data Input: Data is input on the rising edge of the
cycle of WCK when /WE is pulled low
(enabled).
DO7~DO0 Data Output: Data output is synchronized with the RCK clock. Data is obtained at the
rising edge of the RCK clock when /RE is pulled low. The access time is defined from the rising
edge of the RCK cycle.
WCK Write Clock Input: The write data input is synchronized with this clock. Write data is input at
the rising edge of the WCK cycle when /WE is pulled low (enabled). The internal write address
pointer is incremented automatically with this clock input.
RCK Read Clock Input: The read data output is synchronized with this clock. Read data output at
the rising edge of the RCK cycle when /OE is pulled low (enabled). The internal read address pointer
is incremented with this clock input.
/WE Write Enable Input: /WE controls the enabling/disabling of the data input. When /WE is
pulled low, input data is acquired at the rising edge of the WCK cycle. When /WE is pulled high, the
memory does not accept data input. The write address pointer is stopped at the current position. /WE
signal is fetched at the rising edge of the WCK cycle.
384k x8
Memory Cell Array
SRAM
Cache
Timing Generator
& Arbiter
Write
Address
Counter
Read
Address
Counter
Refresh Address
Counter
DI7~
DI0
DO7~
DO0
/OE
RCK
/RRST
/RE
WCK
/WRST
/WE
AL422-03 Block Diagram
Input
Buffer
Write
Data
Register
Read
Data
Register
Output
Buffer
AL422B
AL422B February 20, 2003
14
/RE Read Enable Input: /RE controls the operation of the data output. When /RE is pulled low,
output data is provided at the rising edge of the RCK cycle and the internal read address is
incremented automatically. /RE signal is fetched at the rising edge of the RCK cycle.
/OE Output Enable Input: /OE controls the enabling/disabling of the data output. When /OE is
pulled low, output data is provided at the rising edge of the RCK cycle. When /OE is pulled high,
data output is disabled and the output pins remain at high impedance status. /OE signal is fetched at
the rising edge of RCK cycle.
/WRST Write Reset Input: This reset signal initializes the write address to 0, and is fetched at the
rising edge of the WCK input cycle.
/RRST Write Reset Input: This reset signal initializes the read address to 0, and is fetched at the
rising edge of the RCK input cycle.
TST Test Pin: For testing purpose only. It should be pulled low for normal applications.
DEC: Decoupling cap pin, the DEC pin connects to the 3.3V power with regular 0.1
F bypass
capacitor.
8.1 Memory Operation
Initialization
Apply /WRST and /RRST 0.1ms after power on, then follow the following instructions for normal
operation.
Reset Operation
The reset signal can be given at any time regardless of the /WE, /RE and /OE status, however, they
still need to meet the setup time and hold time requirements with reference to the clock input. When
the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are
enabled again. When /WRST signal is pulled low, the data input address will be set to 0 and the data
in the Input Buffer will be flushed into memory cell array. When /RRST signal is pulled low, the data
output address will be set to 0 and pre-fetch the data from memory cell array to Output Buffer.
Write Operation
Data input DI7~DI0 is written into the write register at the WCK input when /WE is pulled low. The
write data should meet the setup time and hold time requirements with reference to the WCK input
cycle.
AL422B
AL422B February 20, 2003
15
Write operation is prohibited when /WE is pulled high, and the write address pointer is stopped at the
current position. The write address starts from there when the /WE is pulled low again. The /WE
signal needs to meet the setup time and hold time requirements with reference to the WCK input
cycle.
Read Operation
Data output DO7~DO0 is written into the read register at the RCK input when both /RE and /OE are
pulled low. The output data is ready after
T
AC
(access time) from the rising edge of the RCK input
cycle.
The read address pointer is stopped at the current position when /RE is pulled high, and starts there
when /RE is pulled low again.
/OE needs to be pulled low for read operations. When /OE is pulled high, the data outputs will be at
high impedance stage. The read address pointer still increases synchronously with RCK regardless of
the /OE status. The /RE and /OE signals need to meet the setup time and hold time requirements with
reference to the RCK input cycle.
When the new data is read, the read address should be between 128 to 393,247 cycles after the write
address, otherwise the output may not be new data.
8.2 Pin 19 Connection
The 3.3V configuration (direct replacement of the previous AL422V3) is as follows:
8.3 Application Notes
8.3.1 Irregular Read/Write
It is recommended that the WCK and RCK are kept running at least 1MHz at all times. The faster
one of WCK and RCK is used as the DRAM refresh timing clock and has to be kept free running.
When irregular FIFO I/O control is needed, keep the clock free running and use /WE or /RE to
control the I/O as follows:
VDD
DEC
3.3V
AL422B
3.3V
0.1uF
0.1uF
10
19
AL422B
AL422B February 20, 2003
16
The following drawing shows irregular clock and should be avoided:
8.3.2 The Proper Manipulation of FIFO Access
The FIFO memory is designed to allow easy field delay, time-base conversion, and other types of
signal processing. To ensure the expectant data can be read out from the AL422B FIFO, the proper
manipulation on the AL422B FIFO memory is highly recommended

1. The read address should be between 128 to 393,247 cycles after the write address to read the
current field data. (The restriction is indicated in the "Read Operation" Section).

2. The proper FIFO access must make sure after read reset, the read operation will either read all the
old data (last field data) until next read reset, or follow the constraint 1 above to read newly update
data. In any 2 read resets interval, the FIFO access can not read old data (the field data are written
before last write reset), and stop for a period then read the newly update data (even at that time,
write counter is ahead of read counter by more than 128 cycles).

If the FIFO memory manipulations violate the above conditions, some amount of consecutive
unexpected data (old data) will be read at the FIFO data bus.
Data
/WE
AL422-17 Slow Write - Correct
WCK
Data
/WE
AL422-16 Slow Write - Incorrect
WCK
AL422B
AL422B February 20, 2003
17
8.3.3 Single Field Write with Multiple Read Operation
It is one of the functions for FIFO memory that can buffer a field data and do multiple times of fields
read access. In some applications, such as still image capturing, require one field write and multiple
field data read operations. In order not to violate the 128 cycles of write to read delay latency rule,
the write address (pointer) needs to be reset to 0 for the coming multiple read operations so that FIFO
can provide the expectant data at DO bus.
8.3.4 One Field Delay Line (The Old Data Read)
As the design shown in diagram by applying the reset every 1-field cycle (with the common signal for
/WRST and /RRST) and a constant read/write operation (with all /WE, /RE and /OE are tied to
ground), "1 field delay line" timing is shown in timing chart below. When the difference between the
write address and the read address is 0 (the read address and the write address are the same), the old
field data are read as shown in the timing chart.




















AL422 1 Field Delay Line Diagram
8-bit Input
8-bit Output
DI[7:0]
AL422
/WE
WCK
DO[7:0]
/RE
RCK
Reset
Clock
/OE
/RRST
/WRST
AL422B
AL422B February 20, 2003
18
RCK
WCK
/RRST
/WRST
DI7~0
0
AL422-08 1 Field Delay Line Timing Diagram
1
n
cycle 0
cycle 1
cycle n
DO7~0
0
0
Field m
Field m + 1
1
1
cycle 0
t
AC
Data of field m
cycle 1
AL422B
AL422B February 20, 2003
19
9.0 Mechanical Drawing
28 PIN PLASTIC SOP:




CONTACT INFORMATION
Averlogic Technologies Corp.
4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan
Tel: +886 2-27915050
Fax: +886 2-27912132
E-mail:
sales@averlogic.com.tw
URL:
http://www.averlogic.com.tw

Averlogic Technologies, Inc.
90 Great Oaks Blvd. #204, San Jose, CA 95119
USA
Tel: 1 408 361-0400
Fax: 1 408 361-0404
E-mail:
sales@averlogic.com
URL:
http://www.averlogic.com
© 2018 • ChipFind
Контакты
Главная страница