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Datasheet: I2040CF-08SR (Alliance Semiconductor Corporation)

LCD Panel EMI Reduction IC

 

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Alliance Semiconductor Corporation

September 2005
P2040C
rev 1.4
Notice: The information in this document is subject to change without notice.
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
LCD Panel EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 15dB of EMI suppression
Generates a low EMI spread spectrum clock of the
input frequency
50MHz to 170MHz input frequency range
Optimized for 54MHz, 65MHz, 81MHz, 140MHz,
and 162MHz pixel clock frequencies
Internal loop filter minimizes external components
and board space
8 selectable spread ranges, up to 2.2%
SSON# control pin for spread spectrum enable and
disable options
2 selectable modulation rates
Low Cycle-to-cycle jitter
3.3V Operating Voltage
Ultra low power CMOS design
Supports most mobile graphic accelerator and LCD
timing controller specifications
Available in 8 pin SOIC and TSSOP Packages

Product Description
The P2040C is a selectable spread spectrum frequency
modulator designed specifically for digital flat panel
applications. The P2040C reduces electromagnetic
interference (EMI) at the clock source which provides
system wide reduction of EMI of all clock dependent
signals. The P2040C allows significant system cost
savings by reducing the number of circuit board layers and
shielding that are traditionally required to pass EMI
regulations.
The P2040C uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all-digital method. The
P2040C modulates the output of a single PLL in order to
"spread" the bandwidth of a synthesized clock and, more
importantly, decreases the peak amplitudes of its
harmonics. This result in a significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal's bandwidth is called `spread
spectrum clock generation'.

Applications
The P2040C is targeted towards digital flat panel
applications for Notebook PCs, Palm-size PCs, Office
Automation Equipments and LCD Monitors.

Block Diagram















CLKIN
ModOUT
VSS
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
VDD
SSON#
SR0 SR1 MRA

September 2005
P2040C
rev 1.4
LCD Panel EMI Reduction IC 2 of 9
Notice: The information in this document is subject to change without notice.
MRA
SSON#
ModOUT
SR0
1
2
3
4
5
6
7
8
P2040C
CLKIN
SR1
VSS
VDD
1
2
3
4
5
6
7
8
P2040C
CLKIN
SR1
VDD
Pin Configuration












Pin Description
Pin#
Pin
Name
Type
Description
1
CLKIN
I
External reference frequency input. Connect to externally generated reference signal.
2
MRA
I
Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.
3
SR1
I
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
4
VSS
P
Ground to entire chip. Connect to system ground.
5 SSON# I
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum
function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.
6
ModOUT
O
Spread spectrum Clock Output.
7
SR0
I
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
8
VDD
P
Power supply for the entire chip.

Modulation Selection (Commercial) Table 1

Spreading Range
MRA SR1 SR0
54MHz
65MHz
81MHz
140MHz
162MHz
Modulation Rate
0
0
0
1.4%
1.2%
1.0%
0.6%
0.4%
(Fin/80) * 62.49KHz
0
0
1
2.0%
1.9%
1.6%
1.0%
0.8%
(Fin/80) * 62.49KHz
0
1
0
1.1%
0.9%
0.5%
0.3%
0.3%
(Fin/80) * 62.49KHz
0
1
1
1.8%
1.5%
1.0%
0.54%
0.4%
(Fin/80) * 62.49KHz
1
0
0
1.3%
1.3%
1.3%
1.25%
1.1%
(Fin/80) * 20.83KHz
1
0
1
2.2%
2.1%
2.1%
2.0%
1.8%
(Fin/80) * 20.83KHz
1
1
0
1.4%
1.3%
1.4%
1.2%
0.9%
(Fin/80) * 20.83KHz
1
1
1
2.1%
2.1%
2.1%
1.9%
1.4%
(Fin/80) * 20.83KHz

September 2005
P2040C
rev 1.4
LCD Panel EMI Reduction IC 3 of 9
Notice: The information in this document is subject to change without notice.

Spread Spectrum Selection
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without
affecting system performance. The spreading is described as a percentage deviation of the center frequency
(Note: The center frequency is the frequency of the external reference input on CLKIN, Pin 1).

Example: P2040C is designed for high resolution flat panel applications and is able to support panel frequencies from 50MHz
to 170MHz. For a 65MHz pixel clock frequency, a spreading selection of MRA=0, SR1=1 and SR0 =1 provides a percentage
deviation of 1.50% (see Table 1). This result in frequency on ModOUT being swept from 64.03MHz to 65.98MHz at a
modulation rate of 50.77KHz (see Table 1). This particular example (see Figure below) given here is a common EMI reduction
method for notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic
accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
`







Modulated 65MHz signal with
1.5 % deviation and modulation
rate of 50.77KHz. This signal is
connected back to the spread
spectrum input pin (SSIN) of the
graphics accelerator.
1
2
3
4
CLKIN
MRA
SR1
VSS
SR0
5
6
7
8
SSON#
ModOUT
VDD
65MHz from graphics accelerator
+3.3V
0.1F
P2040C
Digital control for the SS enable
or disable

September 2005
P2040C
rev 1.4
LCD Panel EMI Reduction IC 4 of 9
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD, V
IN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
T
STG
Storage temperature
-65 to +125
C
T
A
Operating temperature
-20 to +85
C
T
s
Max. Soldering Temperature (10 sec)
260
C
For SOIC Package
156.5
JA
Thermal Resistance from Junction
to Ambient ( No Air Flow)
For TSSOP Package
124
C/W
T
J
Junction
Temperature
150
C
T
DV
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.

DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25C) unless otherwise stated)
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input low voltage
VSS - 0.3
-
0.8
V
V
IH
Input high voltage
2.0
-
VDD + 0.3
V
I
IL
Input low current (pull-up resistor on inputs SR0, SR1 and MRA)
-
-
-40
A
I
IH
Input high current (pull-down resistor on input SSON#)
-
-
40
A
V
OL
Output low voltage (VDD = 3.3V, I
OL
= 20mA)
-
-
0.4
V
V
OH
Output high voltage (VDD = 3.3V, I
OL
= 20mA)
2.5
-
-
V
I
DD
Static supply current standby mode
-
0.7
-
mA
I
CC
Dynamic supply current (3.3V and 10pF loading)
9
16
22
mA
VDD Operating
Voltage 3.0
3.3
3.6
V
t
ON
Power-up time (first locked cycle after power up)
-
0.18
-
mS
Z
OUT
Clock output impedance
-
50
-

AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
f
IN
Input
frequency
50
170
MHz
t
LH
*
Output rise time (measured at 0.8V to 2.0V)
0.3
0.7
1.0
nS
t
HL
*
Output fall time (measured at 2.0V to 0.8V)
0.3
0.7
1.0
nS
t
JC
Jitter (cycle to cycle)
-
-
360
pS
t
D
Output duty cycle
45
50
55
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF

September 2005
P2040C
rev 1.4
LCD Panel EMI Reduction IC 5 of 9
Notice: The information in this document is subject to change without notice.
Package Information

8-lead (150-mil) SOIC Package


D
E
H
D
A1
A2
A
L
C
B
e

Dimensions
Inches
Millimeters
Symbol
Min
Max
Min
Max
A1 0.004 0.010 0.10
0.25
A 0.053
0.069 1.35 1.75
A2 0.049 0.059 1.25
1.50
B 0.012
0.020 0.31 0.51
C 0.007
0.010 0.18 0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L 0.016
0.050 0.41 1.27
0 8 0 8
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