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Datasheet: I2040AG-08-TR (Alliance Semiconductor Corporation)

LCD Panel EMI Reduction IC

 

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Alliance Semiconductor Corporation

October 2005
P2040A
rev 1.2
Notice: The information in this document is subject to change without notice.
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
LCD Panel EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 20dB of EMI suppression.
Generates a low EMI spread spectrum clock of the
input frequency.
Input frequency range: 30MHz to 100MHz.
Optimized for VGA, SVGA, and higher resolution
XGA LCD Panels.
Internal loop filter minimizes external components
and board space.
Six selectable high spread ranges up to 2%.
Two selectable modulation rates.
SSON# control pin for spread spectrum enable and
disable options.
Low cycle-to-cycle jitter.
Wide operating range.
Low power CMOS design.
Supports most mobile graphic accelerator
specifications.
Products available for automotive temperature
range. (Refer Spread Spectrum Range Selection
Tables)
Available in 8-pin SOIC and TSSOP Packages.

Product Description
The P2040A is a versatile spread spectrum frequency
modulator designed specifically for digital flat panel
applications. The P2040A reduces electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream clock and data
dependent signals. The P2040A allows significant system
cost savings by reducing the number of circuit board
layers ferrite beads, shielding and other passive
components that are traditionally required to pass EMI
regulations.

The P2040A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.

The P2040A modulates the output of a single PLL in
order to "spread" the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal's bandwidth is called `spread
spectrum clock generation'.

Applications
The P2040A is targeted towards digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.

Block Diagram














VDD
CLKIN
ModOUT
VSS
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
SSON#
SR0 SR1 MRA

October 2005
P2040A
rev 1.2
LCD Panel EMI Reduction IC
2 of 9
Notice: The information in this document is subject to change without notice.
MRA
SSON#
ModOUT
1
2
3
4
5
6
7
8
P2040A
CLKIN
SR1
VSS
SR0
VDD
Pin Configuration












Pin Description
Pin#
Pin
Name
Type
Description
1
CLKIN
I
External reference frequency input. Connect to externally generated reference signal.
2
MRA
I
Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.
3
SR1
I
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
4
VSS
P
Ground to entire chip. Connect to system ground.
5 SSON# I
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum
function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.
6
ModOUT
O
Spread spectrum clock output.
7
SR0
I
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
8
VDD
P
Power supply for the entire chip (3.3V)


Modulation Selection (Commercial)
MRA
SR1
SR0
Spreading Range
Modulation Rate (KHz)
0
0
0
1.125
(FIN /40) * 34.72KHz
0
0
1
1.75
(FIN /40) * 34.72KHz
0
1
0
0.75
(FIN /40) * 34.72KHz
0
1
1
1.25
(FIN /40) * 34.72KHz
1
0
0
1.25
(FIN /40) * 20.83KHz
1
0
1
2.00
(FIN /40) * 20.83KHz
1 1 0
Reserved
Reserved
1 1 1
Reserved
Reserved








October 2005
P2040A
rev 1.2
LCD Panel EMI Reduction IC
3 of 9
Notice: The information in this document is subject to change without notice.
Spread Range Selection at 50MHz (Automotive)
MRA
SR1
SR0
Spreading Range
Modulation Rate
0 0 0
1.25
(F
IN
/40) * 34.72KHz
0 0 1
2.00
(F
IN
/40) * 34.72KHz
0 1 0
1.00
(F
IN
/40) * 34.72KHz
0 1 1
1.50
(F
IN
/40) * 34.72KHz
1 0 0
1.25
(F
IN
/40) * 20.83KHz
1 0 1
2.00
(F
IN
/40) * 20.83KHz
1 1 0
1.25
(F
IN
/40) * 20.83KHz
1 1 1
2.00
(F
IN
/40) * 20.83KHz

Spread Range Selection at 70MHz (Automotive)
MRA
SR1
SR0
Spreading Range
Modulation Rate
0 0 0
1.00
(F
IN
/40) * 34.72KHz
0 0 1
1.50
(F
IN
/40) * 34.72KHz
0 1 0
0.70
(F
IN
/40) * 34.72KHz
0 1 1
1.00
(F
IN
/40) * 34.72KHz
1 0 0
1.15
(F
IN
/40) * 20.83KHz
1 0 1
2.00
(F
IN
/40) * 20.83KHz
1 1 0
1.15
(F
IN
/40) * 20.83KHz
1 1 1
1.75
(F
IN
/40) * 20.83KHz

October 2005
P2040A
rev 1.2
LCD Panel EMI Reduction IC
4 of 9
Notice: The information in this document is subject to change without notice.
Spread Spectrum Selection

The Modulation Selection Table defines the possible spread spectrum options. The optimal setting should minimize system
EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center
frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1).

For example, P2040A is designed for high-resolution, flat panel applications and is able to support an XGA (1024 x 768) flat
panel operating at 65MHz (F
IN
) clock speed. A spreading selection of MRA=0, SR1=1 and SR0=0 provides a percentage
deviation of 0.75% from F
IN
. This results in the frequency on ModOUT being swept from 64.51MHz to 65.49MHz at a
modulation rate of 56.24KHz. Refer Modulation Selection Table. The example in the following illustration is a common EMI
reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile
graphic accelerator manufacturers.


Application Schematic for Mobile LCD Graphics Controllers















Modulated 65MHz signal with
0.75 deviation and modulation
rate of 56.24KHz. This signal is
connected back to the spread
spectrum input pin (SSIN) of the
graphics accelerator.
1
2
3
4
CLKIN
MRA
SR1
VSS
SR0
5
6
7
8
SSON#
ModOUT
VDD
65MHz from graphics accelerator
+3.3V
0.1F
P2040A
Digital control for the SS enable
or disable

October 2005
P2040A
rev 1.2
LCD Panel EMI Reduction IC
5 of 9
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD, V
IN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
T
STG
Storage temperature
-65 to +125
C
T
C
Operating temperature-Commercial
0 to 70
C
T
A
Operating temperature Automotive
-40 to +125
C
T
J
Junction
Temperature
150
C
T
DV
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability
.


DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25C) unless otherwise stated)
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input low voltage
VSS - 0.3
-
0.8
V
V
IH
Input high voltage
2.0
-
VDD + 0.3
V
I
IL
Input low current
(pull-up resistor on inputs SR0, SR1 and MRA)
-35 - - A
I
IH
Input high current (pull-down resistor on input SSON#)
-
-
35
A
V
OL
Output low voltage (VDD = 3.3V, I
OL
= 20mA)
-
-
0.4
V
V
OH
Output high voltage (VDD = 3.3V, I
OH
= 20mA)
2.5
-
-
V
I
DD
Static supply current standby
mode
- 0.6 -
mA
I
CC
Dynamic supply current (3.3V and 10pF loading)
7
10
13
mA
VDD Operating
voltage
2.7 3.3 3.7 V
t
ON
Power-up time (first locked cycle after power up)
-
0.18
-
mS
Z
OUT
Clock output impedance
-
50
-


AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
f
IN
Input
frequency
30
-
100
MHz
f
OUT
Output
frequency
30
-
100
MHz
t
LH
*
Output rise time (measured at 0.8V to 2.0V)
0.7
0.9
1.1
nS
t
HL
*
Output fall time (measured at 2.0V to 0.8V)
0.6
0.8
1.0
nS
t
JC
Jitter (cycle to cycle)
-
-
360
pS
t
D
Output duty cycle
45
50
55
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF




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