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Datasheet: ALD110900APA (Advanced Linear Devices)

QUAD/DUAL N-CHANNEL ZERO THRESHOLD EPAD MATCHED PAIR MOSET ARRAY

 

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Advanced Linear Devices
e
EPAD
TM
N A
B L
E D
E
A
DVANCED
L
INEAR
D
EVICES,
I
NC.
GENERAL DESCRIPTION
ALD110800A/ALD110800/ALD110900A/ALD110900 are monolithic
quad/dual N-Channel MOSFETs matched at the factory using ALD's
proven EPAD CMOS technology. These devices are intended for low
voltage, small signal applications. The ALD110800/ALD110900 features
zero threshold voltage, which reduces or eliminates input to output
voltage level shift, including circuits where the signal is referenced to
GND or V+. This feature greatly reduces output signal voltage level
shift and enhances signal operating range, especially for very low
operating voltage environments. With these zero threshold devices an
analog circuit with multiple stages can be constructed to operate at
extremely low supply or bias voltage levels. As an example, an input
amplifier stage operating at 0.2V supply voltage has been demonstrated.
ALD110800A/ALD110800/ALD110900A/ALD110900 matched pair
MOSFETs are designed for exceptional device electrical characteris-
tics matching. As these devices are on the same monolithic chip, they
also exhibit excellent tempco tracking characteristics. They are
versatile as design components for a broad range of analog applica-
tions such as basic building blocks for current sources, differential
amplifier input stages, transmission gates, and multiplexer applications.
Besides matched pair electrical characteristics, each individual
MOSFET also exhibits well controlled parameters, enabling the user
to depend on tight design limits. Even units from different batches
and different date of manufacture have correspondingly well matched
characteristics.
These devices are built for minimum offset voltage and differential
thermal response, and they are designed for switching and amplifying
applications in +0.2V to +10V systems where low input bias current,
low input capacitance and fast switching speed are desired. The V
GS(th)
of these devices are set at +0.0V, which classify them as both enhance-
ment mode and depletion mode devices. When the gate is set at 0.0V,
the drain current = +1
A @ V
DS
=1+0.1V, which allow a class of circuits
with output voltage level biased at or near input voltage level without
voltage level shift. These devices exhibit same well controlled turn-off
and sub-threshold characteristics as standard enhancement mode
MOSFETs.
The ALD110800A/ALD110800/ALD110900A/ALD110900 are MOSFET
devices that feature high input impedance (10
12
) and high DC current
gain (>10
8
). A sample calculation of the DC current gain at a drain
current of 3mA and input leakage current of 30pA at 25
C is = 3mA/
30pA = 100,000,000. For most applications, connect V+ pin to the most
positive voltage potential (or left open unused) and V- and N/C pins to
the most negative voltage potential in the system. All other pins must
have voltages within these voltage limits.
QUAD/DUAL N-CHANNEL ZERO THRESHOLDTM EPAD
MATCHED PAIR MOSFET ARRAY
N/C*
1
2
3
14
15
16
4
13
5
12
N/C*
6
7
8
10
11
G
N1
D
N1
N/C*
D
N4
N/C*
G
N4
9
G
N3
D
N3
D
N2
G
N2
V
+
S
34
S
12
V
-
V
+
V
-
ALD110800
M 4
M 3
M 1
M 2
V
-
V
-
V
-
V
-
V-
G
N1
D
N1
N/C*
S
12
D
N2
G
N2
ALD110900
1
2
3
6
7
8
4
5
M 1
M 2
V-
N/C*
V-
V-
FEATURES
Precision zero threshold voltage mode
Nominal R
DS(ON)
@V
GS
=0.0V of 104K
Matched MOSFET to MOSFET characteristics
Tight lot to lot parametric control
V
GS(th)
match (V
OS
) to 2mV and 10mV
Positive, zero, and negative V
GS(th)
tempco
Low input capacitance
Low input/output leakage currents
APPLICATIONS
Very low voltage analog and digital circuits
Zero power fail safe circuits
Backup battery circuits & power failure detector
Low level voltage clamp & zero crossing detector
Source followers and buffers
Precision current mirrors and current sources
Capacitives probes and sensor interfaces
Charge detectors and charge integrators
Differential amplifier input stage
High side switches
Peak detectors and level shifters
Sample and Hold
Current multipliers
Analog switches / multiplexers
Voltage comparators and level shifters
ALD110800/ALD110800A/ALD110900/ALD110900A
ORDERING INFORMATION
* Contact factory for industrial temp. range or user-specified threshold voltage values
Operating Temperature Range*
0
C to +70
C
0
C to +70
C
16-Pin
16-Pin 8-Pin 8-Pin
Plastic Dip
SOIC Plastic Dip
SOIC
Package
Package Package
Package
ALD110800APC ALD110800ASC ALD110900APA ALD110900ASA
ALD110800PC
ALD110800SC ALD110900PA ALD110900SA
PC, SC PACKAGES
PA, SA PACKAGES
PIN CONFIGURATION
V
GS(th)
= +0.0V
Rev 1.0-0506 2005 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
*N/C pins are internally connected.
Connect to V- to reduce noise
ALD110800/ALD110800A/ALD110900/ALD110900A
Advanced Linear Devices
2
OPERATING ELECTRICAL CHARACTERISTICS
V+ = +5V (or open) V- = GND TA = 25
C unless otherwise specified
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
Notes:
1
Consists of junction leakage currents
ALD110800A / ALD110900A ALD110800/ ALD110900
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
ABSOLUTE MAXIMUM RATINGS
Drain-Source voltage,
V
DS
10.6V
Gate-Source voltage,
V
GS
10.6V
Power dissipation
500 mW
Operating temperature range PA, SA, PC, SC package
0
C to +70
C
Storage temperature range
-65
C to +150
C
Lead temperature, 10 seconds
+260
C
Gate Threshold Voltage
VGS(th)
-0.01
0.00
0.01
-0.02
0.00
0.02
V
IDS =1
A, VDS = 0.1V
Offset Voltage
VOS
1
2
2
10
mV
VGS(th)1-VGS(th)2
Offset Voltage Tempco
TCVOS
5
5
V/
C
VDS1 = VDS2
GateThreshold Voltage Tempco
TCVGS(th)
-1.7
-1.7
mV/
C
ID = 1
A, VDS = 0.1V
0.0
0.0
ID = 20
A, VDS = 0.1V
+1.6
+1.6
ID = 40
A, VDS = 0.1V
On Drain Current
IDS (ON)
12.0
12.0
mA
VGS = +9.5V, VDS = +5V
3.0
3.0
VGS = +4.0V, VDS = +5V
Forward Transconductance
GFS
1.4
1.4
mmho
VGS = +4.0V
VDS = +9.0V
Transconductance Mismatch
GFS
1.8
1.8
%
Output Conductance
GOS
68
68
mho
VGS = +4.0V
VDS = +9.0V
Drain Source On Resistance
RDS (ON)
500
500
VDS = +0.1V
VGS = +4.0V
Drain Source On Resistance
RDS (ON)
104
104
K
VDS = +0.1V
VGS = +0.0V
Drain Source On Resistance
RDS (ON)
5
5
%
VDS = +0.1V
Tolerance
VGS = +4.0V
Drain Source On Resistance
RDS (ON)
0.5
0.5
%
Mismatch
Drain Source Breakdown
BVDSX
10
10
V
IDS = 1.0
A
Voltage
V-= VGS = -1.0V
Drain Source Leakage Current
1
IDS (OFF)
10
400
10
400
pA
VGS = -1.0V, VDS =+5V
V- = -5V
4
4
nA
TA = 125
C
Gate Leakage Current
1
IGSS
5
30
5
30
pA
VDS = 0V VGS = +10V
1
1
nA
TA =125
C
Input Capacitance
CISS
2.5
2.5
pF
Transfer Reverse Capacitance
CRSS
0.1
0.1
pF
Turn-on Delay Time
ton
10
10
ns
V+ = 5V RL= 5K
Turn-off Delay Time
toff
10
10
ns
V+ = 5V RL= 5K
Crosstalk
60
60
dB
f = 100KHz
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