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Document Outline
- ACT 1 Series FPGAs
- Features
- Description
- Product Family Profile
- The Designer and Designer Advantage Systems
- ACT 1 Device Structure
- The ACT 1 Logic Module
- I/O Buffers
- Device Organization
- Probe Pin
- ACT 1 Array Performance
- Ordering Information
- Product Plan
- Device Resources
- Pin Description
- Absolute Maximum Ratings1
- Recommended Operating Conditions
- Electrical Specifications (5V)
- Electrical Specifications (3.3V)
- Package Thermal Characteristics
- General Power Equation
- Functional Timing Tests
- Output Buffer Performance Derating (5V)
- Output Buffer Performance Derating (3.3V)
- ACT 1 Timing Module*
- Predictable Performance: Tight Delay Distributions...
- Timing Characteristics
- Timing Derating Factor (Temperature and Voltage)
- Timing Derating Factor for Designs at Typical Temp...
- Temperature and Voltage Derating Factors (normaliz...
- Temperature and Voltage Derating Factors (normaliz...
- Parameter Measurement
- Sequential Timing Characteristics
- ACT 1 Timing Characteristics (continued)
- ACT 1 Timing Characteristics (continued)
- Package Pin Assignments
- Package Pin Assignments (continued)
- Package Pin Assignments (continued)
- Package Pin Assignments (continued)
- Package Pin Assignments (continued)
- Package Pin Assignments (continued)
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel's
PLICE
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
clock driver with a hardwired distribution network. The
network provides efficient clock distribution with minimum
skew.
and CMOS drive levels. Available packages include plastic
and ceramic J-leaded chip carriers, ceramic and plastic quad
flatpacks, and ceramic pin grid array.
programming and to protect the design from being copied or
reverse engineered.
A d v a n t a g e TM S y s t e m s
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmap
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
3,000
12
6,000
20
Vertical Tracks/Column
PLICE Antifuse Elements
13
13
68 PLCC
68 PLCC
84 PLCC
3.3 V Data Rate (maximum)
55 MHz
55 MHz
modules and distributed horizontal and vertical interconnect
tracks. PLICE antifuses, located at intersections of the
horizontal and vertical tracks, connect logic module inputs
and outputs. During programming, these antifuses are
addressed and programmed to make the connections
required by the circuit application.
chosen for the wide range of functions it implements and for
its efficient use of interconnect routing resources (Figure 2).
functions (NAND, AND, OR, and NOR) in gates of two, three,
or four inputs. Each function may have many versions, with
different combinations of active-low inputs. The logic module
can also implement a variety of D-latches, exclusivity
functions, AND-ORs, and OR-ANDs. No dedicated hardwired
latches or flip-flops are required in the array, since latches
and flip-flops may be constructed from logic modules
wherever needed in the application.
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Outputs sink or
additional I/O buffer specifications.
rows separated by wiring channels. This array is surrounded
by a ring of peripheral circuits including I/O buffers,
testability circuits, and diagnostic probe circuits providing
real-time diagnostic capability. Between rows of logic
modules are routing channels containing sets of segmented
metal tracks with PLICE antifuses. Each channel has 22
signal tracks. Vertical routing is permitted via 13 vertical
tracks per logic module column. The resulting network allows
arbitrary and flexible interconnections between logic
modules and I/O modules.
These pins allow the user to observe any two internal signals
by entering the appropriate net name in the diagnostic
software. Signals may be viewed on a logic analyzer using
Actel's Actionprobe
manner as for masked array products. A typical delay
parameter is multiplied by a derating factor to account for
temperature, voltage, and processing effects. However, in an
ACT 1 array, temperature and voltage effects are less
dramatic than with masked devices. The electrical
characteristics of module interconnections on ACT 1 devices
remain constant over voltage and temperature fluctuations.
worst-case for a standard speed ACT 1 array is only 1.19 to 1,
compared to 2 to 1 for a masked gate array.
programmed gate array cell with four transistors usually
implements only one logic level. In the more complex logic
module (similar to the complexity of a gate array macro) of
an ACT 1 array, implementation of multiple logic levels
within a single module is possible. This eliminates interlevel
wiring and associated RC delays. The effect is termed "net
compression."
1
A10V20 = 2000 Gates (3.3 V)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
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84-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
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Clock input is buffered prior to clocking the logic modules.
This pin can also be used as an I/O.
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are automatically driven LOW by the ALS software.
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/O. To provide Actionprobe capability, the MODE
pin should be terminated to GND through a 10K resistor so
that the MODE pin can be pulled high when required.
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin's probe
capabilities can be permanently disabled to protect the
programmed design's confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin's probe
capabilities can be permanently disabled to protect the
programmed design's confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
Current
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
extremely low current. However, when input voltage is greater
than V
Range
+70
Tolerance
